[PATCH] D48343: [RISCV] Tail calls don't need to save return address

[Sameer AbuAsal via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL335239: [RISCV] Tail calls don't need to save return address (authored by sabuasal, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D48343?vs=152001&id=152296#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D48343

Files:
  llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/trunk/test/MC/RISCV/tail-call.s


Index: llvm/trunk/test/MC/RISCV/tail-call.s
===================================================================
--- llvm/trunk/test/MC/RISCV/tail-call.s
+++ llvm/trunk/test/MC/RISCV/tail-call.s
@@ -17,31 +17,31 @@
 tail foo
 # RELOC: R_RISCV_CALL foo 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: foo, kind:
 tail bar
 # RELOC: R_RISCV_CALL bar 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: bar, kind:
 
 # Ensure that tail calls to functions whose names coincide with register names
 # work.
 
 tail zero
 # RELOC: R_RISCV_CALL zero 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: zero, kind:
 
 tail f1
 # RELOC: R_RISCV_CALL f1 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: f1, kind:
 
 tail ra
 # RELOC: R_RISCV_CALL ra 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: ra, kind:
Index: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -115,8 +115,12 @@
   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
   support::endian::write(OS, Binary, support::little);
 
-  // Emit JALR Ra, Ra, 0
-  TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
+  if (MI.getOpcode() == RISCV::PseudoTAIL)
+    // Emit JALR X0, X6, 0
+    TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
+  else
+    // Emit JALR X1, X1, 0
+    TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
   support::endian::write(OS, Binary, support::little);
 }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D48343.152296.patch
Type: text/x-patch
Size: 1939 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180621/e6a83bae/attachment.bin>