[llvm] r335239 - [RISCV] Tail calls don't need to save return address

[Sameer AbuAsal via llvm-commits]

Author: sabuasal
Date: Thu Jun 21 07:37:09 2018
New Revision: 335239

URL: http://llvm.org/viewvc/llvm-project?rev=335239&view=rev
Log:
[RISCV] Tail calls don't need to save return address

Summary:
 When expanding the PseudoTail in expandFunctionCall() we were using X6
 to save the return address. Since this is a tail call the return
 address is not needed, this patch replaces it with X0 to be ignored.

 This matches the behaviour listed in the ISA V2.2 document page 110.
 tail offset -----> jalr x0, x6, offset

 GCC exhibits the same behavior.

Reviewers: apazos, asb, mgrang

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01

Differential Revision: https://reviews.llvm.org/D48343

Modified:
    llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    llvm/trunk/test/MC/RISCV/tail-call.s

Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp?rev=335239&r1=335238&r2=335239&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp Thu Jun 21 07:37:09 2018
@@ -115,8 +115,12 @@ void RISCVMCCodeEmitter::expandFunctionC
   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
   support::endian::write(OS, Binary, support::little);
 
-  // Emit JALR Ra, Ra, 0
-  TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
+  if (MI.getOpcode() == RISCV::PseudoTAIL)
+    // Emit JALR X0, X6, 0
+    TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
+  else
+    // Emit JALR X1, X1, 0
+    TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
   support::endian::write(OS, Binary, support::little);
 }

Modified: llvm/trunk/test/MC/RISCV/tail-call.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/tail-call.s?rev=335239&r1=335238&r2=335239&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/tail-call.s (original)
+++ llvm/trunk/test/MC/RISCV/tail-call.s Thu Jun 21 07:37:09 2018
@@ -17,12 +17,12 @@
 tail foo
 # RELOC: R_RISCV_CALL foo 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: foo, kind:
 tail bar
 # RELOC: R_RISCV_CALL bar 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: bar, kind:
 
 # Ensure that tail calls to functions whose names coincide with register names
@@ -31,17 +31,17 @@ tail bar
 tail zero
 # RELOC: R_RISCV_CALL zero 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: zero, kind:
 
 tail f1
 # RELOC: R_RISCV_CALL f1 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: f1, kind:
 
 tail ra
 # RELOC: R_RISCV_CALL ra 0x0
 # INSTR: auipc t1, 0
-# INSTR: jalr  t1
+# INSTR: jr  t1
 # FIXUP: fixup A - offset: 0, value: ra, kind: