[PATCH] D48183: [WebAssembly] Modified tablegen defs to have 2 parallel instuction sets.

[Heejin Ahn via Phabricator via llvm-commits]

aheejin added a comment.

Why do we need to change all `def`s to `defm`s and what does it mean to have multiple `(outs)` and `(ins)` within a single instruction?


Repository:
  rL LLVM

https://reviews.llvm.org/D48183