[PATCH] D47980: [InstCombine] Fold (x << y) >> y -> x & (-1 >> y)

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added inline comments.


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Comment at: test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll:898-899
 ; CHECK-NEXT: %1 = sub i32 32, %width
-; CHECK-NEXT: %2 = shl i32 %src, %1
-; CHECK-NEXT: %bfe = lshr i32 %2, %1
+; CHECK-NEXT: %2 = lshr i32 -1, %1
+; CHECK-NEXT: %bfe = and i32 %2, %src
 ; CHECK-NEXT: ret i32 %bfe
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Indeed, the pattern matching in the backend does not recognize this and ends up generating worse code.


Repository:
  rL LLVM

https://reviews.llvm.org/D47980