[PATCH] D47730: [SelectionDAG]Reduce masked data movement chains and memory access widths pt2

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:13008-13009
+  SDValue OR = Store->getValue();
+  if (OR.getOpcode() != ISD::OR)
+    llvm_unreachable("Assuming to be called with an OR operad.");
+  SDValue LoadSD = OR.getOperand(0);
----------------
If you choose to leave the assertion, consider simplifying it into something like

```
assert(OR.getOpcode() == ISD::OR && "Expecting ISD::OR");
```

See the recommendation described in http://llvm.org/docs/ProgrammersManual.html#programmatic-errors 


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:13070-13075
+  //  if (SamePtr) {TODO
+  //    if ((LoadMemSz == StoreMemSz) && (Load->use_size() == 2)) {
+  //      LLVM_DEBUG(dbgs() << "Reduce load width\n");
+  //    }
+  //    LLVM_DEBUG(dbgs() << "Move lower to upper half\n");
+  //  }
----------------
Was this left accidentally? If not, perhaps a single `TODO` comment describing what can be done next will be clearer.


Repository:
  rL LLVM

https://reviews.llvm.org/D47730