[PATCH] D47676: [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity.

[Ganesh Gopalasubramanian via Phabricator via llvm-commits]

GGanesh added inline comments.


================
Comment at: lib/Target/X86/X86ScheduleZnver1.td:96
+// Reference: "Software Optimization Guide for AMD Family 17h Processors"
+def ZnIntegerPRF : RegisterFile<168, [GR8, GR16, GR32, GR64, CCR]>;
+
----------------
I am not sure  why we include CCR register.


================
Comment at: lib/Target/X86/X86ScheduleZnver1.td:100
+def ZnFPU     : ProcResGroup<[ZnFPU0, ZnFPU1, ZnFPU2, ZnFPU3]> {
+let BufferSize=36;
+}
----------------
This number is fine.


================
Comment at: lib/Target/X86/X86ScheduleZnver1.td:111
+// Reference: "Software Optimization Guide for AMD Family 17h Processors"
+def ZnRCU : RetireControlUnit<192, 8>;
+
----------------
The retire unit is shared between integer and FP ops. In SMT mode it is 96 entry per thread. So, I think we shall consider only 96 entry as a conservative value.


================
Comment at: lib/Target/X86/X86ScheduleZnver1.td:113
+
+// FIXME: there are 72 read buffers and 44 write buffers.
+
----------------
I assume these are the load/store queue entries. The FPU has
1. 44 entry Load Queue
2. 72 Out of Order Loads
3. 44 entry Store Queue
So, we are concerned only about the queues, we can have only 44 marked for LD and ST.



Repository:
  rL LLVM

https://reviews.llvm.org/D47676