[PATCH] D47589: [RISCV] Add codegen support for atomic load/stores with RV32A

[JF Bastien via Phabricator via llvm-commits]

jfb added a comment.

Making it the behavior we choose is fine with me. I just understood your comment to mean that you wanted to give this semantics, and that's more work than just stating the semantics you want.

In https://reviews.llvm.org/D47589#1118021, @efriedma wrote:

> LangRef should be fixed... it doesn't make sense to have undefined behavior with respect to a static property of the instruction, and I think it's out-of-date with recent changes.  (Support for unaligned atomic load/store was recently added as an extension for AVR.)


Say I have two TUs which share an atomic location, but have a different idea of its alignment. They both access that location, one with libcall and one with an instruction. That's clearly broken. Can this happen?


https://reviews.llvm.org/D47589