[PATCH] D47589: [RISCV] Add codegen support for atomic load/stores with RV32A

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

LangRef should be fixed... it doesn't make sense to have undefined behavior with respect to a static property of the instruction, and I think it's out-of-date with recent changes.  (Support for unaligned atomic load/store was recently added as an extension for AVR.)


https://reviews.llvm.org/D47589