[PATCH] D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning.

[Amara Emerson via Phabricator via llvm-commits]

aemerson updated this revision to Diff 149282.
aemerson retitled this revision from "[GlobalISel][Legalizer] Fix i1s being sign extended instead of zero-extended" to "[AArch64][GlobalISel] Zero-extend s1 values when returning.".
aemerson edited the summary of this revision.
aemerson added a comment.

New patch now only zero-extends for stores, removing the use of getBooleanContents.

We already have test coverage for the store zero-extension.

The return issue is fixed in AArch64CallLowering instead.


Repository:
  rL LLVM

https://reviews.llvm.org/D47425

Files:
  lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  lib/Target/AArch64/AArch64CallLowering.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll


Index: test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
===================================================================
--- test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1859,3 +1859,14 @@
   store %agg.nested { i32 1, i32 1, %agg.inner { i16 2, i8 3, %agg.inner.inner {i64 5, i64 8} }, i32 13}, %agg.nested *%ptr
   ret void
 }
+
+define i1 @return_i1_zext() {
+; AAPCS ABI says that booleans can only be 1 or 0, so we need to zero-extend.
+; CHECK-LABEL: name: return_i1_zext
+; CHECK: [[CST:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[CST]](s1)
+; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
+; CHECK: $w0 = COPY [[ANYEXT]](s32)
+; CHECK: RET_ReallyLR implicit $w0
+  ret i1 true
+}
Index: lib/Target/AArch64/AArch64CallLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64CallLowering.cpp
+++ lib/Target/AArch64/AArch64CallLowering.cpp
@@ -229,9 +229,15 @@
   assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
   bool Success = true;
   if (VReg) {
+    MachineRegisterInfo &MRI = MF.getRegInfo();
+    if (MRI.getType(VReg).getSizeInBits() == 1) {
+      // We zero-extend i1s to i8.
+      unsigned ZExt = MRI.createGenericVirtualRegister(LLT::scalar(8));
+      MIRBuilder.buildZExt(ZExt, VReg);
+      VReg = ZExt;
+    }
     const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
     CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
-    MachineRegisterInfo &MRI = MF.getRegInfo();
     auto &DL = F.getParent()->getDataLayout();
 
     ArgInfo OrigArg{VReg, Val->getType()};
Index: lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -726,17 +726,7 @@
         WideTy != LLT::scalar(8))
       return UnableToLegalize;
 
-    const auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
-    switch (TLI.getBooleanContents(false, false)) {
-    case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
-      widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_SEXT);
-      break;
-    case TargetLoweringBase::ZeroOrOneBooleanContent:
-      widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ZEXT);
-      break;
-    default:
-      widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ANYEXT);
-    }
+    widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ZEXT);
     MIRBuilder.recordInsertion(&MI);
     return Legalized;
   }


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