[PATCH] D47568: [Power9] Do the add-imm peephole for pseudo instruction DFLOADf32/DFLOADf64 and the store pair

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai requested changes to this revision.
nemanjai added inline comments.
This revision now requires changes to proceed.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:2091
+    assert(MI.getOperand(2).isReg() &&
+           (MI.getOperand(1).isImm() || MI.getOperand(1).isCPI()) &&
            "D-form op must have register and immediate operands");
----------------
This is not adequate. We don't only convert this for constant pool loads, it will crash with something like this (also please add this as a test case):
```
float FArr[10];

float getF() {
  return FArr[3] + 3.4f;
}
```
I think it's probably a good idea to implement something like:
```
#ifndef NDEBUG
static bool isAnImmediateOperand(const MachineOperand &MO) {
  return MO.isCPI() || MO.isGlobal() || MO.isImm();
}
#endif
```
and use that in this (and similar) assert(s).


https://reviews.llvm.org/D47568