[PATCH] D47568: [Power9] Do the add-imm peephole for pseudo instruction DFLOADf32/DFLOADf64 and the store pair

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: hfinkel, nemanjai.
Herald added subscribers: kbarton, hiraditya.

If the arch is https://reviews.llvm.org/P9, we will select the DFLOADf32/DFLOADf64 pseudo instruction when we are loading a floating, and expand it post RA basing on the register pressure. However, we miss to do the add-imm peephole for these pseudo instruction.


https://reviews.llvm.org/D47568

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/CodeGen/PowerPC/mcm-12.ll
  llvm/test/CodeGen/PowerPC/toc-float.ll

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