[PATCH] D45395: [RISCV] Lower the tail pseudoinstruction

[Mandeep Singh Grang via Phabricator via llvm-commits]

mgrang added a comment.

Thanks for the pointer Alex. I guess what I was doing incorrect was specifying GPRTC as the reg class in the PseudoInstExpansion which made the tablegen trip.

  def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTC:$rs1), [(Tail GPRTC:$rs1)]>,
                           PseudoInstExpansion<(JALR X0, GPRTC:$rs1, 0)>;

With your suggestion PseudoTAILIndirect is not an almost exact replica of PseudoCALLIndirect. Thanks again!


https://reviews.llvm.org/D45395