[llvm] r332970 - [mips] Correct the predicates of the cache and pref instructions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue May 22 03:55:05 PDT 2018
Author: sdardis
Date: Tue May 22 03:55:05 2018
New Revision: 332970
URL: http://llvm.org/viewvc/llvm-project?rev=332970&view=rev
Log:
[mips] Correct the predicates of the cache and pref instructions
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46949
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips/valid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=332970&r1=332969&r2=332970&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Tue May 22 03:55:05 2018
@@ -1052,16 +1052,14 @@ let DecoderNamespace = "MicroMips" in {
ISA_MICROMIPS, ASE_EVA;
def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,
ISA_MICROMIPS, ASE_EVA;
-}
-let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
+
let DecoderMethod = "DecodeCacheOpMM" in {
- def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
- CACHE_PREF_FM_MM<0x08, 0x6>;
- def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
- CACHE_PREF_FM_MM<0x18, 0x2>;
+ def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
+ CACHE_PREF_FM_MM<0x08, 0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
+ CACHE_PREF_FM_MM<0x18, 0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
}
-}
-let DecoderNamespace = "MicroMips" in {
+
let DecoderMethod = "DecodePrefeOpMM" in {
def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA;
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=332970&r1=332969&r2=332970&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Tue May 22 03:55:05 2018
@@ -888,9 +888,7 @@ let AdditionalPredicates = [NotInMicroMi
def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
-}
-def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
-let AdditionalPredicates = [NotInMicroMips] in {
+ def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
}
@@ -943,8 +941,8 @@ let AdditionalPredicates = [NotInMicroMi
def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
}
def NAL; // BAL with rd=0
-def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
+ def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=332970&r1=332969&r2=332970&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue May 22 03:55:05 2018
@@ -2454,10 +2454,12 @@ class CacheOp<string instr_asm, Operand
let DecoderMethod = "DecodeCacheOp";
}
-def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>,
- INSN_MIPS3_32_NOT_32R6_64R6;
-def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>,
- INSN_MIPS3_32_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>,
+ INSN_MIPS3_32_NOT_32R6_64R6;
+ def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>,
+ INSN_MIPS3_32_NOT_32R6_64R6;
+}
// FIXME: We are missing the prefx instruction.
def ROL : MipsAsmPseudoInst<(outs),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
Modified: llvm/trunk/test/MC/Mips/micromips/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/valid.s?rev=332970&r1=332969&r2=332970&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/valid.s Tue May 22 03:55:05 2018
@@ -187,7 +187,9 @@ tlti $9, 17767 # CHECK: tlt
tltiu $9, 17767 # CHECK: tltiu $9, 17767 # encoding: [0x41,0x49,0x45,0x67]
tnei $9, 17767 # CHECK: tnei $9, 17767 # encoding: [0x41,0x89,0x45,0x67]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
+ # CHECK-NEXT: # <MCInst #{{.*}} CACHE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
+ # CHECK-NEXT: # <MCInst #{{.*}} PREF_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x08,0x00]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00]
pause # CHECK: pause # encoding: [0x00,0x00,0x28,0x00]
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=332970&r1=332969&r2=332970&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Tue May 22 03:55:05 2018
@@ -46,6 +46,7 @@
break 7 # CHECK: break 7 # encoding: [0x00,0x07,0x00,0x07]
break 7, 5 # CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x47]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
+ # CHECK-NEXT: # <MCInst #{{.*}} CACHE_MMR6
clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c]
clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18]
@@ -113,6 +114,7 @@
or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]
ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2]
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
+ # CHECK-NEXT: # <MCInst #{{.*}} PREF_MMR6
sb16 $3, 4($16) # CHECK: sb16 $3, 4($16) # encoding: [0x89,0x84]
seb $3, $4 # CHECK: seb $3, $4 # encoding: [0x00,0x64,0x2b,0x3c]
seb $3 # CHECK: seb $3, $3 # encoding: [0x00,0x63,0x2b,0x3c]
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=332970&r1=332969&r2=332970&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Tue May 22 03:55:05 2018
@@ -66,6 +66,7 @@ a:
bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01]
bovc $2, $4, 4 # CHECK: bovc $2, $4, 4 # encoding: [0x20,0x82,0x00,0x01]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25]
+ # CHECK-NEXT: # <MCInst #{{.*}} CACHE_R6
ceil.w.d $f11,$f24 # CHECK: ceil.w.d $f11, $f24 # encoding: [0x46,0x20,0xc2,0xce]
# CHECK: # <MCInst #{{.*}} CEIL_W_D64
ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
@@ -152,6 +153,7 @@ a:
# CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
# CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35]
+ # CHECK-NEXT: # <MCInst #{{.*}} PREF_R6
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push
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