[llvm] r331961 - [X86] ptwrite intrinsic
Evgenii Stepanov via llvm-commits
llvm-commits at lists.llvm.org
Thu May 10 11:39:10 PDT 2018
Hi,
this change makes almost all sanitizer bots unhappy.
UBSan (sour bool):
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/17958/steps/check-llvm%20ubsan/logs/stdio
MSan (uninit, but stack trace is truncated):
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/4545/steps/check-llvm%20msan/logs/stdio
On Thu, May 10, 2018 at 12:26 AM, Gabor Buella via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: gbuella
> Date: Thu May 10 00:26:05 2018
> New Revision: 331961
>
> URL: http://llvm.org/viewvc/llvm-project?rev=331961&view=rev
> Log:
> [X86] ptwrite intrinsic
>
> Reviewers: craig.topper, RKSimon
>
> Reviewed By: craig.topper, RKSimon
>
> Differential Revision: https://reviews.llvm.org/D46539
>
> Added:
> llvm/trunk/test/CodeGen/X86/ptwrite32-intrinsic.ll
> llvm/trunk/test/CodeGen/X86/ptwrite64-intrinsic.ll
> Modified:
> llvm/trunk/include/llvm/IR/IntrinsicsX86.td
> llvm/trunk/lib/Support/Host.cpp
> llvm/trunk/lib/Target/X86/X86.td
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
> llvm/trunk/lib/Target/X86/X86InstrSystem.td
> llvm/trunk/lib/Target/X86/X86Subtarget.h
>
> Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/
> llvm/IR/IntrinsicsX86.td?rev=331961&r1=331960&r2=331961&view=diff
> ============================================================
> ==================
> --- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)
> +++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Thu May 10 00:26:05 2018
> @@ -6425,3 +6425,13 @@ let TargetPrefix = "x86" in {
> def int_x86_movdir64b : GCCBuiltin<"__builtin_ia32_movdir64b">,
> Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], []>;
> }
> +
> +//===------------------------------------------------------
> ----------------===//
> +// PTWrite - Write data to processor trace pocket
> +
> +let TargetPrefix = "x86" in {
> + def int_x86_ptwrite32 : GCCBuiltin<"__builtin_ia32_ptwrite32">,
> + Intrinsic<[], [llvm_i32_ty], []>;
> + def int_x86_ptwrite64 : GCCBuiltin<"__builtin_ia32_ptwrite64">,
> + Intrinsic<[], [llvm_i64_ty], []>;
> +}
>
> Modified: llvm/trunk/lib/Support/Host.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/
> Support/Host.cpp?rev=331961&r1=331960&r2=331961&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Support/Host.cpp (original)
> +++ llvm/trunk/lib/Support/Host.cpp Thu May 10 00:26:05 2018
> @@ -1286,6 +1286,11 @@ bool sys::getHostCPUFeatures(StringMap<b
> Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
> Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
>
> + bool HasLeaf14 = MaxLevel >= 0x14 &&
> + !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX,
> &EDX);
> +
> + Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
> +
> return true;
> }
> #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
>
> Modified: llvm/trunk/lib/Target/X86/X86.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> X86/X86.td?rev=331961&r1=331960&r2=331961&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/X86/X86.td (original)
> +++ llvm/trunk/lib/Target/X86/X86.td Thu May 10 00:26:05 2018
> @@ -232,6 +232,8 @@ def FeatureCLZERO : SubtargetFeature<"c
> "Enable Cache Line Zero">;
> def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
> "Enable Cache Demote">;
> +def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
> + "Support ptwrite instruction">;
> def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
> "Support MPX instructions">;
> def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
> @@ -624,23 +626,25 @@ class GoldmontProc<string Name> : ProcMo
> ]>;
> def : GoldmontProc<"goldmont">;
>
> -class GoldmontPlusProc<string Name> : ProcModel<Name, SLMModel,
> - GLMFeatures.Value, [
> - ProcIntelGLP,
> +def GLPFeatures : ProcessorFeatures<GLMFeatures.Value, [
> + FeaturePTWRITE,
> FeatureRDPID,
> FeatureSGX
> ]>;
> +
> +class GoldmontPlusProc<string Name> : ProcModel<Name, SLMModel,
> + GLPFeatures.Value, [
> + ProcIntelGLP
> +]>;
> def : GoldmontPlusProc<"goldmont-plus">;
>
> class TremontProc<string Name> : ProcModel<Name, SLMModel,
> - GLMFeatures.Value, [
> + GLPFeatures.Value, [
> ProcIntelTRM,
> FeatureCLDEMOTE,
> FeatureGFNI,
> FeatureMOVDIRI,
> FeatureMOVDIR64B,
> - FeatureRDPID,
> - FeatureSGX,
> FeatureWAITPKG
> ]>;
> def : TremontProc<"tremont">;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> X86/X86InstrInfo.td?rev=331961&r1=331960&r2=331961&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu May 10 00:26:05 2018
> @@ -894,6 +894,7 @@ def HasCLZERO : Predicate<"Subtarget-
> def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">;
> def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">;
> def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">;
> +def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">;
> def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
> def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
> def HasMPX : Predicate<"Subtarget->hasMPX()">;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> X86/X86InstrSystem.td?rev=331961&r1=331960&r2=331961&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Thu May 10 00:26:05 2018
> @@ -688,18 +688,21 @@ let Predicates = [In64BitMode, HasRDPID]
>
>
> //===-------------------------------------------------------
> ---------------===//
> -// PTWRITE Instruction
> +// PTWRITE Instruction - Write Data to a Processor Trace Packet
> let SchedRW = [WriteSystem] in {
> -
> def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
> - "ptwrite{l}\t$dst", []>, XS;
> + "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32
> addr:$dst))]>, XS,
> + Requires<[HasPTWRITE]>;
> def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
> - "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;
> + "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64
> addr:$dst))]>, XS,
> + Requires<[In64BitMode, HasPTWRITE]>;
>
> def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
> - "ptwrite{l}\t$dst", []>, XS;
> + "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
> + Requires<[HasPTWRITE]>;
> def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
> - "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;
> + "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>,
> XS,
> + Requires<[In64BitMode, HasPTWRITE]>;
> } // SchedRW
>
> //===-------------------------------------------------------
> ---------------===//
> @@ -719,4 +722,4 @@ let SchedRW = [WriteSystem] in {
> let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
> def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,
> Requires<[HasPCONFIG]>;
> -} // SchedRW
> \ No newline at end of file
> +} // SchedRW
>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> X86/X86Subtarget.h?rev=331961&r1=331960&r2=331961&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu May 10 00:26:05 2018
> @@ -215,6 +215,9 @@ protected:
> /// Processor has MOVDIR64B instruction (direct store 64 bytes).
> bool HasMOVDIR64B;
>
> + /// Processor has ptwrite instruction.
> + bool HasPTWRITE;
> +
> /// Processor has Prefetch with intent to Write instruction
> bool HasPREFETCHWT1;
>
> @@ -593,6 +596,7 @@ public:
> bool hasCLDEMOTE() const { return HasCLDEMOTE; }
> bool hasMOVDIRI() const { return HasMOVDIRI; }
> bool hasMOVDIR64B() const { return HasMOVDIR64B; }
> + bool hasPTWRITE() const { return HasPTWRITE; }
> bool isSHLDSlow() const { return IsSHLDSlow; }
> bool isPMULLDSlow() const { return IsPMULLDSlow; }
> bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
>
> Added: llvm/trunk/test/CodeGen/X86/ptwrite32-intrinsic.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/X86/ptwrite32-intrinsic.ll?rev=331961&view=auto
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/X86/ptwrite32-intrinsic.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/ptwrite32-intrinsic.ll Thu May 10
> 00:26:05 2018
> @@ -0,0 +1,56 @@
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+ptwrite | FileCheck
> %s --check-prefix=X86
> +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ptwrite |
> FileCheck %s --check-prefix=X86_64
> +
> +define void @test_ptwrite(i32 %value) {
> +; X86-LABEL: test_ptwrite:
> +; X86: # %bb.0: # %entry
> +; X86-NEXT: ptwritel {{[0-9]+}}(%esp)
> +; X86-NEXT: retl
> +;
> +; X86_64-LABEL: test_ptwrite:
> +; X86_64: # %bb.0: # %entry
> +; X86_64-NEXT: ptwritel %edi
> +; X86_64-NEXT: retq
> +entry:
> + call void @llvm.x86.ptwrite32(i32 %value)
> + ret void
> +}
> +
> +define void @test_ptwrite2(i32 %x) {
> +; X86-LABEL: test_ptwrite2:
> +; X86: # %bb.0: # %entry
> +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
> +; X86-NEXT: incl %eax
> +; X86-NEXT: ptwritel %eax
> +; X86-NEXT: retl
> +;
> +; X86_64-LABEL: test_ptwrite2:
> +; X86_64: # %bb.0: # %entry
> +; X86_64-NEXT: incl %edi
> +; X86_64-NEXT: ptwritel %edi
> +; X86_64-NEXT: retq
> +entry:
> + %value = add i32 %x, 1
> + call void @llvm.x86.ptwrite32(i32 %value)
> + ret void
> +}
> +
> +define void @test_ptwrite32p(i32* %pointer) {
> +; X86-LABEL: test_ptwrite32p:
> +; X86: # %bb.0: # %entry
> +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
> +; X86-NEXT: ptwritel (%eax)
> +; X86-NEXT: retl
> +;
> +; X86_64-LABEL: test_ptwrite32p:
> +; X86_64: # %bb.0: # %entry
> +; X86_64-NEXT: ptwritel (%rdi)
> +; X86_64-NEXT: retq
> +entry:
> + %value = load i32, i32* %pointer, align 4
> + call void @llvm.x86.ptwrite32(i32 %value)
> + ret void
> +}
> +
> +declare void @llvm.x86.ptwrite32(i32)
>
> Added: llvm/trunk/test/CodeGen/X86/ptwrite64-intrinsic.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/X86/ptwrite64-intrinsic.ll?rev=331961&view=auto
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/X86/ptwrite64-intrinsic.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/ptwrite64-intrinsic.ll Thu May 10
> 00:26:05 2018
> @@ -0,0 +1,25 @@
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ptwrite |
> FileCheck %s
> +
> +define void @test_ptwrite64(i64 %value) {
> +; CHECK-LABEL: test_ptwrite64:
> +; CHECK: # %bb.0: # %entry
> +; CHECK-NEXT: ptwriteq %rdi
> +; CHECK-NEXT: retq
> +entry:
> + call void @llvm.x86.ptwrite64(i64 %value)
> + ret void
> +}
> +
> +define void @test_ptwrite64p(i64* %pointer) {
> +; CHECK-LABEL: test_ptwrite64p:
> +; CHECK: # %bb.0: # %entry
> +; CHECK-NEXT: ptwriteq (%rdi)
> +; CHECK-NEXT: retq
> +entry:
> + %value = load i64, i64* %pointer, align 8
> + call void @llvm.x86.ptwrite64(i64 %value)
> + ret void
> +}
> +
> +declare void @llvm.x86.ptwrite64(i64)
>
>
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