<div dir="ltr">Hi,<div><br></div><div>this change makes almost all sanitizer bots unhappy.</div><div><br></div><div>UBSan (sour bool):</div><div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/17958/steps/check-llvm%20ubsan/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/17958/steps/check-llvm%20ubsan/logs/stdio</a><br></div><div><br></div><div>MSan (uninit, but stack trace is truncated):</div><div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/4545/steps/check-llvm%20msan/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/4545/steps/check-llvm%20msan/logs/stdio</a><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, May 10, 2018 at 12:26 AM, Gabor Buella via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: gbuella<br>
Date: Thu May 10 00:26:05 2018<br>
New Revision: 331961<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=331961&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=331961&view=rev</a><br>
Log:<br>
[X86] ptwrite intrinsic<br>
<br>
Reviewers: craig.topper, RKSimon<br>
<br>
Reviewed By: craig.topper, RKSimon<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D46539" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D46539</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/<wbr>ptwrite32-intrinsic.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>ptwrite64-intrinsic.ll<br>
Modified:<br>
llvm/trunk/include/llvm/IR/<wbr>IntrinsicsX86.td<br>
llvm/trunk/lib/Support/Host.<wbr>cpp<br>
llvm/trunk/lib/Target/X86/X86.<wbr>td<br>
llvm/trunk/lib/Target/X86/<wbr>X86InstrInfo.td<br>
llvm/trunk/lib/Target/X86/<wbr>X86InstrSystem.td<br>
llvm/trunk/lib/Target/X86/<wbr>X86Subtarget.h<br>
<br>
Modified: llvm/trunk/include/llvm/IR/<wbr>IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=331961&r1=331960&r2=331961&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/IR/IntrinsicsX86.td?rev=<wbr>331961&r1=331960&r2=331961&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/IR/<wbr>IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/<wbr>IntrinsicsX86.td Thu May 10 00:26:05 2018<br>
@@ -6425,3 +6425,13 @@ let TargetPrefix = "x86" in {<br>
def int_x86_movdir64b : GCCBuiltin<"__builtin_ia32_<wbr>movdir64b">,<br>
Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], []>;<br>
}<br>
+<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+// PTWrite - Write data to processor trace pocket<br>
+<br>
+let TargetPrefix = "x86" in {<br>
+ def int_x86_ptwrite32 : GCCBuiltin<"__builtin_ia32_<wbr>ptwrite32">,<br>
+ Intrinsic<[], [llvm_i32_ty], []>;<br>
+ def int_x86_ptwrite64 : GCCBuiltin<"__builtin_ia32_<wbr>ptwrite64">,<br>
+ Intrinsic<[], [llvm_i64_ty], []>;<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Support/Host.<wbr>cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=331961&r1=331960&r2=331961&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>Support/Host.cpp?rev=331961&<wbr>r1=331960&r2=331961&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Support/Host.<wbr>cpp (original)<br>
+++ llvm/trunk/lib/Support/Host.<wbr>cpp Thu May 10 00:26:05 2018<br>
@@ -1286,6 +1286,11 @@ bool sys::getHostCPUFeatures(<wbr>StringMap<b<br>
Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;<br>
Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;<br>
<br>
+ bool HasLeaf14 = MaxLevel >= 0x14 &&<br>
+ !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);<br>
+<br>
+ Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);<br>
+<br>
return true;<br>
}<br>
#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86.<wbr>td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=331961&r1=331960&r2=331961&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86.td?rev=331961&r1=<wbr>331960&r2=331961&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86.<wbr>td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86.<wbr>td Thu May 10 00:26:05 2018<br>
@@ -232,6 +232,8 @@ def FeatureCLZERO : SubtargetFeature<"c<br>
"Enable Cache Line Zero">;<br>
def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",<br>
"Enable Cache Demote">;<br>
+def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",<br>
+ "Support ptwrite instruction">;<br>
def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",<br>
"Support MPX instructions">;<br>
def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",<br>
@@ -624,23 +626,25 @@ class GoldmontProc<string Name> : ProcMo<br>
]>;<br>
def : GoldmontProc<"goldmont">;<br>
<br>
-class GoldmontPlusProc<string Name> : ProcModel<Name, SLMModel,<br>
- GLMFeatures.Value, [<br>
- ProcIntelGLP,<br>
+def GLPFeatures : ProcessorFeatures<GLMFeatures.<wbr>Value, [<br>
+ FeaturePTWRITE,<br>
FeatureRDPID,<br>
FeatureSGX<br>
]>;<br>
+<br>
+class GoldmontPlusProc<string Name> : ProcModel<Name, SLMModel,<br>
+ GLPFeatures.Value, [<br>
+ ProcIntelGLP<br>
+]>;<br>
def : GoldmontPlusProc<"goldmont-<wbr>plus">;<br>
<br>
class TremontProc<string Name> : ProcModel<Name, SLMModel,<br>
- GLMFeatures.Value, [<br>
+ GLPFeatures.Value, [<br>
ProcIntelTRM,<br>
FeatureCLDEMOTE,<br>
FeatureGFNI,<br>
FeatureMOVDIRI,<br>
FeatureMOVDIR64B,<br>
- FeatureRDPID,<br>
- FeatureSGX,<br>
FeatureWAITPKG<br>
]>;<br>
def : TremontProc<"tremont">;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=331961&r1=331960&r2=331961&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86InstrInfo.td?rev=<wbr>331961&r1=331960&r2=331961&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86InstrInfo.td Thu May 10 00:26:05 2018<br>
@@ -894,6 +894,7 @@ def HasCLZERO : Predicate<"Subtarget-<br>
def HasCLDEMOTE : Predicate<"Subtarget-><wbr>hasCLDEMOTE()">;<br>
def HasMOVDIRI : Predicate<"Subtarget-><wbr>hasMOVDIRI()">;<br>
def HasMOVDIR64B : Predicate<"Subtarget-><wbr>hasMOVDIR64B()">;<br>
+def HasPTWRITE : Predicate<"Subtarget-><wbr>hasPTWRITE()">;<br>
def FPStackf32 : Predicate<"!Subtarget-><wbr>hasSSE1()">;<br>
def FPStackf64 : Predicate<"!Subtarget-><wbr>hasSSE2()">;<br>
def HasMPX : Predicate<"Subtarget->hasMPX()<wbr>">;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86InstrSystem.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=331961&r1=331960&r2=331961&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86InstrSystem.td?rev=<wbr>331961&r1=331960&r2=331961&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86InstrSystem.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86InstrSystem.td Thu May 10 00:26:05 2018<br>
@@ -688,18 +688,21 @@ let Predicates = [In64BitMode, HasRDPID]<br>
<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
-// PTWRITE Instruction<br>
+// PTWRITE Instruction - Write Data to a Processor Trace Packet<br>
let SchedRW = [WriteSystem] in {<br>
-<br>
def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),<br>
- "ptwrite{l}\t$dst", []>, XS;<br>
+ "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS,<br>
+ Requires<[HasPTWRITE]>;<br>
def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),<br>
- "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;<br>
+ "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS,<br>
+ Requires<[In64BitMode, HasPTWRITE]>;<br>
<br>
def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),<br>
- "ptwrite{l}\t$dst", []>, XS;<br>
+ "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,<br>
+ Requires<[HasPTWRITE]>;<br>
def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),<br>
- "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;<br>
+ "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,<br>
+ Requires<[In64BitMode, HasPTWRITE]>;<br>
} // SchedRW<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
@@ -719,4 +722,4 @@ let SchedRW = [WriteSystem] in {<br>
let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in<br>
def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,<br>
Requires<[HasPCONFIG]>;<br>
-} // SchedRW<br>
\ No newline at end of file<br>
+} // SchedRW<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86Subtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=331961&r1=331960&r2=331961&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86Subtarget.h?rev=331961&<wbr>r1=331960&r2=331961&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86Subtarget.h (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86Subtarget.h Thu May 10 00:26:05 2018<br>
@@ -215,6 +215,9 @@ protected:<br>
/// Processor has MOVDIR64B instruction (direct store 64 bytes).<br>
bool HasMOVDIR64B;<br>
<br>
+ /// Processor has ptwrite instruction.<br>
+ bool HasPTWRITE;<br>
+<br>
/// Processor has Prefetch with intent to Write instruction<br>
bool HasPREFETCHWT1;<br>
<br>
@@ -593,6 +596,7 @@ public:<br>
bool hasCLDEMOTE() const { return HasCLDEMOTE; }<br>
bool hasMOVDIRI() const { return HasMOVDIRI; }<br>
bool hasMOVDIR64B() const { return HasMOVDIR64B; }<br>
+ bool hasPTWRITE() const { return HasPTWRITE; }<br>
bool isSHLDSlow() const { return IsSHLDSlow; }<br>
bool isPMULLDSlow() const { return IsPMULLDSlow; }<br>
bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/<wbr>ptwrite32-intrinsic.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ptwrite32-intrinsic.ll?rev=331961&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/ptwrite32-<wbr>intrinsic.ll?rev=331961&view=<wbr>auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>ptwrite32-intrinsic.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>ptwrite32-intrinsic.ll Thu May 10 00:26:05 2018<br>
@@ -0,0 +1,56 @@<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.<wbr>py<br>
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+ptwrite | FileCheck %s --check-prefix=X86<br>
+; RUN: llc < %s -mtriple=x86_64-unknown-<wbr>unknown -mattr=+ptwrite | FileCheck %s --check-prefix=X86_64<br>
+<br>
+define void @test_ptwrite(i32 %value) {<br>
+; X86-LABEL: test_ptwrite:<br>
+; X86: # %bb.0: # %entry<br>
+; X86-NEXT: ptwritel {{[0-9]+}}(%esp)<br>
+; X86-NEXT: retl<br>
+;<br>
+; X86_64-LABEL: test_ptwrite:<br>
+; X86_64: # %bb.0: # %entry<br>
+; X86_64-NEXT: ptwritel %edi<br>
+; X86_64-NEXT: retq<br>
+entry:<br>
+ call void @llvm.x86.ptwrite32(i32 %value)<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_ptwrite2(i32 %x) {<br>
+; X86-LABEL: test_ptwrite2:<br>
+; X86: # %bb.0: # %entry<br>
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
+; X86-NEXT: incl %eax<br>
+; X86-NEXT: ptwritel %eax<br>
+; X86-NEXT: retl<br>
+;<br>
+; X86_64-LABEL: test_ptwrite2:<br>
+; X86_64: # %bb.0: # %entry<br>
+; X86_64-NEXT: incl %edi<br>
+; X86_64-NEXT: ptwritel %edi<br>
+; X86_64-NEXT: retq<br>
+entry:<br>
+ %value = add i32 %x, 1<br>
+ call void @llvm.x86.ptwrite32(i32 %value)<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_ptwrite32p(i32* %pointer) {<br>
+; X86-LABEL: test_ptwrite32p:<br>
+; X86: # %bb.0: # %entry<br>
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
+; X86-NEXT: ptwritel (%eax)<br>
+; X86-NEXT: retl<br>
+;<br>
+; X86_64-LABEL: test_ptwrite32p:<br>
+; X86_64: # %bb.0: # %entry<br>
+; X86_64-NEXT: ptwritel (%rdi)<br>
+; X86_64-NEXT: retq<br>
+entry:<br>
+ %value = load i32, i32* %pointer, align 4<br>
+ call void @llvm.x86.ptwrite32(i32 %value)<br>
+ ret void<br>
+}<br>
+<br>
+declare void @llvm.x86.ptwrite32(i32)<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/<wbr>ptwrite64-intrinsic.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ptwrite64-intrinsic.ll?rev=331961&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/ptwrite64-<wbr>intrinsic.ll?rev=331961&view=<wbr>auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>ptwrite64-intrinsic.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>ptwrite64-intrinsic.ll Thu May 10 00:26:05 2018<br>
@@ -0,0 +1,25 @@<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.<wbr>py<br>
+; RUN: llc < %s -mtriple=x86_64-unknown-<wbr>unknown -mattr=+ptwrite | FileCheck %s<br>
+<br>
+define void @test_ptwrite64(i64 %value) {<br>
+; CHECK-LABEL: test_ptwrite64:<br>
+; CHECK: # %bb.0: # %entry<br>
+; CHECK-NEXT: ptwriteq %rdi<br>
+; CHECK-NEXT: retq<br>
+entry:<br>
+ call void @llvm.x86.ptwrite64(i64 %value)<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_ptwrite64p(i64* %pointer) {<br>
+; CHECK-LABEL: test_ptwrite64p:<br>
+; CHECK: # %bb.0: # %entry<br>
+; CHECK-NEXT: ptwriteq (%rdi)<br>
+; CHECK-NEXT: retq<br>
+entry:<br>
+ %value = load i64, i64* %pointer, align 8<br>
+ call void @llvm.x86.ptwrite64(i64 %value)<br>
+ ret void<br>
+}<br>
+<br>
+declare void @llvm.x86.ptwrite64(i64)<br>
<br>
<br>
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</blockquote></div><br></div>