[PATCH] D46679: [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


================
Comment at: lib/Target/AArch64/SVEInstrFormats.td:1153
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
----------------
javed.absar wrote:
> Please add Sched<[WriteVLDx]> in all such cases.
I think so far we excluded scheduling info for SVE instructions, as there is no information available publicly on how resources/units will be structured on actual HW (i.e. if they are shared with the NEON vector units). 

If we want to add resources at this stage, it might be safer to add SVE specific resources, which each model could tie to the respective units in the implementation. But I suppose we will have to refine the scheduling info in any case once real HW becomes available. What do you think?


https://reviews.llvm.org/D46679