[PATCH] D46679: [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions.

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


================
Comment at: lib/Target/AArch64/SVEInstrFormats.td:1153
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
----------------
Please add Sched<[WriteVLDx]> in all such cases.


https://reviews.llvm.org/D46679