[PATCH] D46634: RegAllocGreedy-ForceGlobal should use number of Allocatable registers

[Muhammad Sarahneh via Phabricator via llvm-commits]

smohser updated this revision to Diff 145887.
smohser added a reviewer: atrick.
smohser added a comment.

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Repository:
  rL LLVM

https://reviews.llvm.org/D46634

Files:
  lib/CodeGen/RegAllocGreedy.cpp


Index: lib/CodeGen/RegAllocGreedy.cpp
===================================================================
--- lib/CodeGen/RegAllocGreedy.cpp
+++ lib/CodeGen/RegAllocGreedy.cpp
@@ -700,7 +700,7 @@
     bool ReverseLocal = TRI->reverseLocalAssignment();
     const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
     bool ForceGlobal = !ReverseLocal &&
-      (Size / SlotIndex::InstrDist) > (2 * RC.getNumRegs());
+      (Size / SlotIndex::InstrDist) > (2 * RegClassInfo.getNumAllocatableRegs(&RC));
 
     if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
         LIS->intervalIsInOneMBB(*LI)) {


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