[PATCH] D46634: RegAllocGreedy-ForceGlobal should use number of Allocatable registers

[Muhammad Sarahneh via Phabricator via llvm-commits]

smohser created this revision.
Herald added subscribers: llvm-commits, qcolombet, MatzeB.

RegAllocGreedy decides to allocate global and split ranges based on registers number in the register class, which includes preassigned registers and some cases unusable registers (if your register class includes registers for multiple cores), when it should only consider the allocatable registers only.


Repository:
  rL LLVM

https://reviews.llvm.org/D46634

Files:
  lib/CodeGen/RegAllocGreedy.cpp


Index: lib/CodeGen/RegAllocGreedy.cpp
===================================================================
--- lib/CodeGen/RegAllocGreedy.cpp
+++ lib/CodeGen/RegAllocGreedy.cpp
@@ -700,7 +700,7 @@
     bool ReverseLocal = TRI->reverseLocalAssignment();
     const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
     bool ForceGlobal = !ReverseLocal &&
-      (Size / SlotIndex::InstrDist) > (2 * RC.getNumRegs());
+      (Size / SlotIndex::InstrDist) > (2 * RegClassInfo.getNumAllocatableRegs(&RC));
 
     if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
         LIS->intervalIsInOneMBB(*LI)) {


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