[PATCH] D46477: [AARCH64] Change max stores for memcpy/memmov/memset and gang up loads and stores (for memcpy) for pairing.

[Sirish Pande via Phabricator via llvm-commits]

SirishP created this revision.
SirishP added reviewers: eli.friedman, davide, evandro, sebpop, javed.absar.
Herald added subscribers: hiraditya, kristof.beyls, eraman, rengolin.

This is continuation of https://reviews.llvm.org/D45098. Besides changing max stores for memcpy/memmove and memset, this patch also gangs up loads and stores for pairing (in case of memcpy). We address only memcpy and not other memory operations, because in mempy source and destination addresses are disjoint and hence no alias analysis is required to disambiguate loads and stores.

Each target defines numbers of loads and stores to be ganged up. For Aarch64, it is set at 4. Other targets have defaulted to 0, and hence no effect.


Repository:
  rL LLVM

https://reviews.llvm.org/D46477

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-2012-05-07-MemcpyAlignBug.ll
  llvm/test/CodeGen/AArch64/arm64-memcpy-inline.ll
  llvm/test/CodeGen/AArch64/arm64-memset-to-bzero.ll
  llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
  llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
  llvm/test/CodeGen/AArch64/arm64-virtual_base.ll
  llvm/test/CodeGen/AArch64/mergestores_noimplicitfloat.ll
  llvm/test/CodeGen/ARM/memcpy-inline.ll

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