[PATCH] D46221: [RISCV] Implement MC layer support for the tail pseudoinstruction

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

These are the possibilities for parameter passing on RV32I/RV64I:

1. Directly in a single register
2. Directly in a pair of registers
3. Directly in a register stack location
4. Indirectly in a register
5. Indirectly in a stack location

Because long double (fp128) and i128 are larger than 2*XLEN, they are passed indirectly and options 1-3 don't apply. Therefore the address of the value will be passed in a register, or if not available then the address is put on the stack. In order to pass indirectly, space on the stack often needs to be allocated in order to store the value. You're seeing this in the example code you pasted. You can see the logic for handling this in RISCVISelLowering.cpp if you grep for CCValAssign::Indirect.

Thanks for catching this issue. Rejecting tailcall optimisation when CCInfo.getNextStackOffset() != 0 isn't quit enough, we need to also reject it if any of the CCValAssign ArgsLocs are passed CCValAssign::Indirect (I can see the ARM's isEligibleForTailCall does that check too).


https://reviews.llvm.org/D46221