[PATCH] D46311: [AArch64] added FP16 vcvth intrinsic support

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer requested changes to this revision.
SjoerdMeijer added a comment.
This revision now requires changes to proceed.

Sorry, I had one more look, see question inlined.



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Comment at: lib/Target/AArch64/AArch64InstrFormats.td:7804
+  def HDr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
+                                FPR16, FPR64, vecshiftR16, asm, []> {
+    let Inst{21-16} = imm{5-0};
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Does this need to be vecshiftR32 and thus accept values [1,32]? If that's the case, we also need to update the tests.


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Comment at: lib/Target/AArch64/AArch64InstrFormats.td:7822
   def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
-                              FPR64, FPR64, vecshiftR64, asm, []> {
+                              FPR64, FPR64, vecshiftR16, asm, []> {
     let Inst{21-16} = imm{5-0};
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We don't need to change this?


Repository:
  rL LLVM

https://reviews.llvm.org/D46311