[PATCH] D46311: [AArch64] added FP16 vcvth intrinsic support

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer accepted this revision.
SjoerdMeijer added a comment.
This revision is now accepted and ready to land.

Thanks, looks good to me now. One more nit inlined, but no need for another review.



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Comment at: lib/Target/AArch64/AArch64InstrFormats.td:5982
     let Predicates = [HasNEON, HasFullFP16] in {
-    def #NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
-      []>;
+    def #NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm, []>; 
     } // Predicates = [HasNEON, HasFullFP16]
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No changes were made here, so can you keep the old formatting?


Repository:
  rL LLVM

https://reviews.llvm.org/D46311