[llvm] r331355 - [X86] Fix scheduling info for VMPSADBWYrmi.

[Andrea Di Biagio via llvm-commits]

I was expecting only this change:

```
-  let ResourceCycles = [1,2,1,7];
+  let ResourceCycles = [1,2,1];
```

Are the other changes intentional?


On Wed, May 2, 2018 at 2:40 PM, Clement Courbet via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: courbet
> Date: Wed May  2 06:40:48 2018
> New Revision: 331355
>
> URL: http://llvm.org/viewvc/llvm-project?rev=331355&view=rev
> Log:
> [X86] Fix scheduling info for VMPSADBWYrmi.
>
> https://reviews.llvm.org/D46356
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> X86/X86SchedBroadwell.td?rev=331355&r1=331354&r2=331355&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Wed May  2 06:40:48
> 2018
> @@ -11,7 +11,6 @@
>  // scheduling and other instruction cost heuristics.
>  //
>  //===-------------------------------------------------------
> ---------------===//
> -
>  def BroadwellModel : SchedMachineModel {
>    // All x86 instructions are modeled as a single micro-op, and BW can
> decode 4
>    // instructions per cycle.
> @@ -156,9 +155,9 @@ def  : WriteRes<WriteFStore,       [BWPo
>  def  : WriteRes<WriteFMove,        [BWPort5]>;
>
>  defm : BWWriteResPair<WriteFAdd,   [BWPort1],  3, [1], 1, 5>; // Floating
> point add/sub.
> -defm : BWWriteResPair<WriteFAddY,  [BWPort1],  3, [1], 1, 6>; // Floating
> point add/sub (YMM/ZMM).
> +defm : BWWriteResPair<WriteFAddY,  [BWPort1],  3, [1], 1, 7>; // Floating
> point add/sub (YMM/ZMM).
>  defm : BWWriteResPair<WriteFCmp,   [BWPort1],  3, [1], 1, 5>; // Floating
> point compare.
> -defm : BWWriteResPair<WriteFCmpY,  [BWPort1],  3, [1], 1, 6>; // Floating
> point compare (YMM/ZMM).
> +defm : BWWriteResPair<WriteFCmpY,  [BWPort1],  3, [1], 1, 7>; // Floating
> point compare (YMM/ZMM).
>  defm : BWWriteResPair<WriteFCom,   [BWPort1],  3>; // Floating point
> compare to flags.
>  defm : BWWriteResPair<WriteFMul,   [BWPort0],  5, [1], 1, 5>; // Floating
> point multiplication.
>  defm : BWWriteResPair<WriteFMulY,  [BWPort0],  5, [1], 1, 7>; // Floating
> point multiplication (YMM/ZMM).
> @@ -1369,8 +1368,20 @@ def BWWriteResGroup101 : SchedWriteRes<[
>  }
>  def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
>                                               "ILD_F(16|32|64)m",
> +                                             "VADDPDYrm",
> +                                             "VADDPSYrm",
> +                                             "VADDSUBPDYrm",
> +                                             "VADDSUBPSYrm",
> +                                             "VCMPPDYrmi",
> +                                             "VCMPPSYrmi",
>                                               "VCVTPS2DQYrm",
> -                                             "VCVTTPS2DQYrm")>;
> +                                             "VCVTTPS2DQYrm",
> +                                             "VMAX(C?)PDYrm",
> +                                             "VMAX(C?)PSYrm",
> +                                             "VMIN(C?)PDYrm",
> +                                             "VMIN(C?)PSYrm",
> +                                             "VSUBPDYrm",
> +                                             "VSUBPSYrm")>;
>
>  def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
>    let Latency = 9;
> @@ -1643,7 +1654,7 @@ def: InstRW<[BWWriteResGroup137_1], (ins
>  def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
>    let Latency = 13;
>    let NumMicroOps = 4;
> -  let ResourceCycles = [1,2,1,7];
> +  let ResourceCycles = [1,2,1];
>  }
>  def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
>
>
>
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