<div dir="ltr"><div>I was expecting only this change:<br><br>```<br>
- let ResourceCycles = [1,2,1,7];<br>
+ let ResourceCycles = [1,2,1];
<br>```<br><br></div>Are the other changes intentional?<br><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, May 2, 2018 at 2:40 PM, Clement Courbet via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: courbet<br>
Date: Wed May 2 06:40:48 2018<br>
New Revision: 331355<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=331355&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=331355&view=rev</a><br>
Log:<br>
[X86] Fix scheduling info for VMPSADBWYrmi.<br>
<br>
<a href="https://reviews.llvm.org/D46356" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D46356</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/<wbr>X86SchedBroadwell.td<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86SchedBroadwell.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=331355&r1=331354&r2=331355&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86SchedBroadwell.td?rev=<wbr>331355&r1=331354&r2=331355&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86SchedBroadwell.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86SchedBroadwell.td Wed May 2 06:40:48 2018<br>
@@ -11,7 +11,6 @@<br>
// scheduling and other instruction cost heuristics.<br>
//<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
-<br>
def BroadwellModel : SchedMachineModel {<br>
// All x86 instructions are modeled as a single micro-op, and BW can decode 4<br>
// instructions per cycle.<br>
@@ -156,9 +155,9 @@ def : WriteRes<WriteFStore, [BWPo<br>
def : WriteRes<WriteFMove, [BWPort5]>;<br>
<br>
defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub.<br>
-defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).<br>
+defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 7>; // Floating point add/sub (YMM/ZMM).<br>
defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare.<br>
-defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM).<br>
+defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 7>; // Floating point compare (YMM/ZMM).<br>
defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags.<br>
defm : BWWriteResPair<WriteFMul, [BWPort0], 5, [1], 1, 5>; // Floating point multiplication.<br>
defm : BWWriteResPair<WriteFMulY, [BWPort0], 5, [1], 1, 7>; // Floating point multiplication (YMM/ZMM).<br>
@@ -1369,8 +1368,20 @@ def BWWriteResGroup101 : SchedWriteRes<[<br>
}<br>
def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",<br>
"ILD_F(16|32|64)m",<br>
+ "VADDPDYrm",<br>
+ "VADDPSYrm",<br>
+ "VADDSUBPDYrm",<br>
+ "VADDSUBPSYrm",<br>
+ "VCMPPDYrmi",<br>
+ "VCMPPSYrmi",<br>
"VCVTPS2DQYrm",<br>
- "VCVTTPS2DQYrm")>;<br>
+ "VCVTTPS2DQYrm",<br>
+ "VMAX(C?)PDYrm",<br>
+ "VMAX(C?)PSYrm",<br>
+ "VMIN(C?)PDYrm",<br>
+ "VMIN(C?)PSYrm",<br>
+ "VSUBPDYrm",<br>
+ "VSUBPSYrm")>;<br>
<br>
def BWWriteResGroup102 : SchedWriteRes<[BWPort5,<wbr>BWPort23]> {<br>
let Latency = 9;<br>
@@ -1643,7 +1654,7 @@ def: InstRW<[BWWriteResGroup137_1], (ins<br>
def BWWriteResGroup138 : SchedWriteRes<[BWPort0,<wbr>BWPort5,BWPort23]> {<br>
let Latency = 13;<br>
let NumMicroOps = 4;<br>
- let ResourceCycles = [1,2,1,7];<br>
+ let ResourceCycles = [1,2,1];<br>
}<br>
def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;<br>
<br>
<br>
<br>
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</blockquote></div><br></div>