[PATCH] D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.

[Clement Courbet via Phabricator via llvm-commits]

courbet marked 5 inline comments as done.
courbet added inline comments.


================
Comment at: lib/Target/Mips/MipsScheduleGeneric.td:77
   let Latency = 33;
-  let ResourceCycles = [1, 33];
+  let ResourceCycles = [33];
 }
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sdardis wrote:
> courbet wrote:
> > @sdardis Can you have a look at this one ? Thanks.
> Bug. The divide unit in the generic model is supposed to be separate from the ALU. It's a hold-over from when I developed the generic model, as I cribbed it from the P5600 model with has two units working on the divide according to the model.
> 
> This change is correct.
Thanks !


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Comment at: lib/Target/X86/X86SchedBroadwell.td:1657
   let NumMicroOps = 4;
-  let ResourceCycles = [1,2,1,7];
+  let ResourceCycles = [1,2,1];
 }
----------------
RKSimon wrote:
> This fix can be committed now in its own commit.
Will do.


Repository:
  rL LLVM

https://reviews.llvm.org/D46356