[PATCH] D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.

[Simon Dardis via Phabricator via llvm-commits]

sdardis added inline comments.


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Comment at: lib/Target/Mips/MipsScheduleGeneric.td:77
   let Latency = 33;
-  let ResourceCycles = [1, 33];
+  let ResourceCycles = [33];
 }
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courbet wrote:
> @sdardis Can you have a look at this one ? Thanks.
Bug. The divide unit in the generic model is supposed to be separate from the ALU. It's a hold-over from when I developed the generic model, as I cribbed it from the P5600 model with has two units working on the divide according to the model.

This change is correct.


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Comment at: lib/Target/Mips/MipsScheduleGeneric.td:82
   let Latency = 31;
-  let ResourceCycles = [1, 31];
+  let ResourceCycles = [31];
 }
----------------
As is this.


Repository:
  rL LLVM

https://reviews.llvm.org/D46356