[PATCH] D46269: [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: test/MC/AArch64/SVE/ldnt1b-diagnostics.s:13
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnt1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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samparker wrote:
> Just curious, but what happens if MUL VL is excluded? Is it just syntactic sugar?
If the 'mul vl' is omitted you get an invalid operand on the ']' token. Basically, the ', mul vl' is parsed and re-inserted as a literal string token (in parseOptionalMulVl), which is then matched to the literal string in the instruction definition.


https://reviews.llvm.org/D46269