[PATCH] D46269: [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions.

[Sam Parker via Phabricator via llvm-commits]

samparker accepted this revision.
samparker added a comment.
This revision is now accepted and ready to land.

LGTM, cheers.



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Comment at: test/MC/AArch64/SVE/ldnt1b-diagnostics.s:13
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnt1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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Just curious, but what happens if MUL VL is excluded? Is it just syntactic sugar?


https://reviews.llvm.org/D46269