[PATCH] D46215: [AArch64] Support reserving x16 and x17 register

[Roland McGrath via Phabricator via llvm-commits]

mcgrathr accepted this revision.
mcgrathr added a comment.
This revision is now accepted and ready to land.

I don't know the backend or the register allocator at all but this looks like a thorough parallel of the existing model for `-ffixed-x18`.



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Comment at: llvm/lib/Target/AArch64/AArch64Subtarget.cpp:155
     : AArch64GenSubtargetInfo(TT, CPU, FS),
-      ReserveX18(AArch64::isX18ReservedByDefault(TT)), IsLittle(LittleEndian),
-      TargetTriple(TT), FrameLowering(),
+      ReserveX18(AArch64::isX18ReservedByDefault(TT)),
+      IsLittle(LittleEndian), TargetTriple(TT), FrameLowering(),
----------------
We could imagine dying default reserved-x16 or reserved-x17 to -mcmodel=kernel (as we do with TIPIDR_EL1 e.g.) but that's probably not worthwhile since we want the flexibility to change what we're using in the kernel.


================
Comment at: llvm/test/CodeGen/AArch64/arm64-platform-reg.ll:24
 
+; CHECK-RESERVE-X16-NOT: ldr fp
+; CHECK-RESERVE-X16-NOT: ldr x16
----------------
Possibly worth separately testing combinations of reserve-{x16,x17,x18}.  It would be a bug if max register pressure used any when more than one is enabled.


Repository:
  rL LLVM

https://reviews.llvm.org/D46215