[llvm] r330928 - [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 26 01:19:53 PDT 2018
Author: s.desmalen
Date: Thu Apr 26 01:19:53 2018
New Revision: 330928
URL: http://llvm.org/viewvc/llvm-project?rev=330928&view=rev
Log:
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load instructions.
Patch [2/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46023
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
llvm/trunk/test/MC/AArch64/SVE/ld1b.s
llvm/trunk/test/MC/AArch64/SVE/ld1d.s
llvm/trunk/test/MC/AArch64/SVE/ld1h.s
llvm/trunk/test/MC/AArch64/SVE/ld1sb.s
llvm/trunk/test/MC/AArch64/SVE/ld1sh.s
llvm/trunk/test/MC/AArch64/SVE/ld1sw.s
llvm/trunk/test/MC/AArch64/SVE/ld1w.s
llvm/trunk/test/MC/AArch64/SVE/ldff1b.s
llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1d.s
llvm/trunk/test/MC/AArch64/SVE/ldff1h.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s
llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldff1w.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Thu Apr 26 01:19:53 2018
@@ -106,7 +106,89 @@ let Predicates = [HasSVE] in {
defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d, "ld3d", simm4Scale3MulVl>;
defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4Scale4MulVl>;
- // continuous store with immediates
+ // Gathers using unscaled 32-bit offsets, e.g.
+ // ld1h z0.s, p0/z, [x0, z0.s, uxtw]
+ defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+ defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+ defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+ defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+ defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+ defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+ defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+ defm GLDFF1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+ defm GLD1W : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+ defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
+
+ // Gathers using scaled 32-bit offsets, e.g.
+ // ld1h z0.s, p0/z, [x0, z0.s, uxtw #1]
+ defm GLD1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
+ defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
+ defm GLD1H_S : sve_mem_32b_gld_sv_32_scaled<0b0110, "ld1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
+ defm GLDFF1H_S : sve_mem_32b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
+ defm GLD1W : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
+ defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
+
+ // Gathers using unscaled 64-bit offsets, e.g.
+ // ld1h z0.d, p0/z, [x0, z0.d]
+ defm GLD1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb">;
+ defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb">;
+ defm GLD1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0010, "ld1b">;
+ defm GLDFF1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0011, "ldff1b">;
+ defm GLD1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0100, "ld1sh">;
+ defm GLDFF1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0101, "ldff1sh">;
+ defm GLD1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0110, "ld1h">;
+ defm GLDFF1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0111, "ldff1h">;
+ defm GLD1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1000, "ld1sw">;
+ defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw">;
+ defm GLD1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1010, "ld1w">;
+ defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w">;
+ defm GLD1D : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d">;
+ defm GLDFF1D : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d">;
+
+ // Gathers using scaled 64-bit offsets, e.g.
+ // ld1h z0.d, p0/z, [x0, z0.d, lsl #1]
+ defm GLD1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0100, "ld1sh", ZPR64ExtLSL16>;
+ defm GLDFF1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0101, "ldff1sh", ZPR64ExtLSL16>;
+ defm GLD1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0110, "ld1h", ZPR64ExtLSL16>;
+ defm GLDFF1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0111, "ldff1h", ZPR64ExtLSL16>;
+ defm GLD1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw", ZPR64ExtLSL32>;
+ defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>;
+ defm GLD1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1010, "ld1w", ZPR64ExtLSL32>;
+ defm GLDFF1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w", ZPR64ExtLSL32>;
+ defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", ZPR64ExtLSL64>;
+ defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", ZPR64ExtLSL64>;
+
+ // Gathers using unscaled 32-bit offsets unpacked in 64-bits elements, e.g.
+ // ld1h z0.d, p0/z, [x0, z0.d, uxtw]
+ defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLD1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLD1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLDFF1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLD1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLD1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLDFF1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLD1D : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+ defm GLDFF1D : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
+
+ // Gathers using scaled 32-bit offsets unpacked in 64-bits elements, e.g.
+ // ld1h z0.d, p0/z, [x0, z0.d, uxtw #1]
+ defm GLD1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
+ defm GLDFF1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0101, "ldff1sh",ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
+ defm GLD1H_D : sve_mem_64b_gld_sv_32_scaled<0b0110, "ld1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
+ defm GLDFF1H_D : sve_mem_64b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
+ defm GLD1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1000, "ld1sw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
+ defm GLDFF1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1001, "ldff1sw",ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
+ defm GLD1W_D : sve_mem_64b_gld_sv_32_scaled<0b1010, "ld1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
+ defm GLDFF1W_D : sve_mem_64b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
+ defm GLD1D : sve_mem_64b_gld_sv_32_scaled<0b1110, "ld1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
+ defm GLDFF1D : sve_mem_64b_gld_sv_32_scaled<0b1111, "ldff1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
+
+ // contiguous store with immediates
defm ST1B_IMM : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Thu Apr 26 01:19:53 2018
@@ -760,3 +760,132 @@ multiclass sve_mem_eld_si<bits<2> sz, bi
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
(!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
}
+
+//===----------------------------------------------------------------------===//
+// SVE Memory - 32-bit Gather and Unsized Contiguous Group
+//===----------------------------------------------------------------------===//
+
+// bit xs is '1' if offsets are signed
+// bit scaled is '1' if the offsets are scaled
+class sve_mem_32b_gld_sv<bits<4> opc, bit xs, bit scaled, string asm,
+ RegisterOperand zprext>
+: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+ asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Rn;
+ bits<5> Zm;
+ bits<5> Zt;
+ let Inst{31-25} = 0b1000010;
+ let Inst{24-23} = opc{3-2};
+ let Inst{22} = xs;
+ let Inst{21} = scaled;
+ let Inst{20-16} = Zm;
+ let Inst{15} = 0b0;
+ let Inst{14-13} = opc{1-0};
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+ let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+ let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_32b_gld_sv_32_scaled<bits<4> opc, string asm,
+ RegisterOperand sxtw_opnd,
+ RegisterOperand uxtw_opnd> {
+ def _UXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 0, 1, asm, uxtw_opnd>;
+ def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 1, 1, asm, sxtw_opnd>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+}
+
+multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
+ RegisterOperand sxtw_opnd,
+ RegisterOperand uxtw_opnd> {
+ def _UXTW_REAL : sve_mem_32b_gld_sv<opc, 0, 0, asm, uxtw_opnd>;
+ def _SXTW_REAL : sve_mem_32b_gld_sv<opc, 1, 0, asm, sxtw_opnd>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+}
+
+
+//===----------------------------------------------------------------------===//
+// SVE Memory - 64-bit Gather Group
+//===----------------------------------------------------------------------===//
+
+// bit xs is '1' if offsets are signed
+// bit scaled is '1' if the offsets are scaled
+// bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
+class sve_mem_64b_gld_sv<bits<4> opc, bit xs, bit scaled, bit lsl, string asm,
+ RegisterOperand zprext>
+: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+ asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Rn;
+ bits<5> Zm;
+ bits<5> Zt;
+ let Inst{31-25} = 0b1100010;
+ let Inst{24-23} = opc{3-2};
+ let Inst{22} = xs;
+ let Inst{21} = scaled;
+ let Inst{20-16} = Zm;
+ let Inst{15} = lsl;
+ let Inst{14-13} = opc{1-0};
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+ let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+ let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_64b_gld_sv_32_scaled<bits<4> opc, string asm,
+ RegisterOperand sxtw_opnd,
+ RegisterOperand uxtw_opnd> {
+ def _UXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 0, 1, 0, asm, uxtw_opnd>;
+ def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 0, asm, sxtw_opnd>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+}
+
+multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm,
+ RegisterOperand sxtw_opnd,
+ RegisterOperand uxtw_opnd> {
+ def _UXTW_REAL : sve_mem_64b_gld_sv<opc, 0, 0, 0, asm, uxtw_opnd>;
+ def _SXTW_REAL : sve_mem_64b_gld_sv<opc, 1, 0, 0, asm, sxtw_opnd>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+}
+
+multiclass sve_mem_64b_gld_sv2_64_scaled<bits<4> opc, string asm,
+ RegisterOperand zprext> {
+ def _SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 1, asm, zprext>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
+}
+
+multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm> {
+ def _REAL : sve_mem_64b_gld_sv<opc, 1, 0, 1, asm, ZPR64ExtLSL8>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
+ (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
+}
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1b.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1b.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1b.s Thu Apr 26 01:19:53 2018
@@ -138,3 +138,33 @@ ld1b { z23.d }, p3/z, [x13, x8]
// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 4d 68 a4 <unknown>
+
+ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x40,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 84 <unknown>
+
+ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x40,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 84 <unknown>
+
+ld1b { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1b { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xdf,0x5f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 5f c4 <unknown>
+
+ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x55,0x15,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 15 c4 <unknown>
+
+ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x55,0x55,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 55 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1d.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1d.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1d.s Thu Apr 26 01:19:53 2018
@@ -42,3 +42,39 @@ ld1d { z23.d }, p3/z, [x13, x8, lsl #
// CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 4d e8 a5 <unknown>
+
+ld1d { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1d { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xdf,0xdf,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df df c5 <unknown>
+
+ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+// CHECK-INST: ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+// CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 cd e8 c5 <unknown>
+
+ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x55,0x95,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 95 c5 <unknown>
+
+ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x55,0xd5,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 d5 c5 <unknown>
+
+ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+// CHECK-INST: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+// CHECK-ENCODING: [0x00,0x40,0xa0,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 a0 c5 <unknown>
+
+ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+// CHECK-INST: ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+// CHECK-ENCODING: [0x00,0x40,0xe0,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 e0 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1h.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1h.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1h.s Thu Apr 26 01:19:53 2018
@@ -102,3 +102,63 @@ ld1h { z23.d }, p3/z, [x13, x8, lsl #
// CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 4d e8 a4 <unknown>
+
+ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x40,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 80 84 <unknown>
+
+ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x40,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 c0 84 <unknown>
+
+ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+// CHECK-INST: ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+// CHECK-ENCODING: [0xff,0x5f,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 5f bf 84 <unknown>
+
+ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+// CHECK-INST: ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+// CHECK-ENCODING: [0xff,0x5f,0xff,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 5f ff 84 <unknown>
+
+ld1h { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1h { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xdf,0xdf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df df c4 <unknown>
+
+ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-INST: ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 cd e8 c4 <unknown>
+
+ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x55,0x95,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 95 c4 <unknown>
+
+ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x55,0xd5,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 d5 c4 <unknown>
+
+ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+// CHECK-INST: ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+// CHECK-ENCODING: [0x00,0x40,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 a0 c4 <unknown>
+
+ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+// CHECK-INST: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+// CHECK-ENCODING: [0x00,0x40,0xe0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 e0 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1sb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sb.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sb.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sb.s Thu Apr 26 01:19:53 2018
@@ -108,3 +108,33 @@ ld1sb { z23.d }, p3/z, [x13, x8]
// CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 4d 88 a5 <unknown>
+
+ld1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x00,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 00 84 <unknown>
+
+ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x00,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 40 84 <unknown>
+
+ld1sb { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1sb { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0x9f,0x5f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 5f c4 <unknown>
+
+ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x15,0x15,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 15 c4 <unknown>
+
+ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x15,0x55,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 55 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1sh.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sh.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sh.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sh.s Thu Apr 26 01:19:53 2018
@@ -72,3 +72,63 @@ ld1sh { z23.d }, p3/z, [x13, x8, lsl
// CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 4d 08 a5 <unknown>
+
+ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x00,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 80 84 <unknown>
+
+ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x00,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 c0 84 <unknown>
+
+ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+// CHECK-INST: ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+// CHECK-ENCODING: [0xff,0x1f,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f bf 84 <unknown>
+
+ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+// CHECK-INST: ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+// CHECK-ENCODING: [0xff,0x1f,0xff,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f ff 84 <unknown>
+
+ld1sh { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1sh { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0x9f,0xdf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f df c4 <unknown>
+
+ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-INST: ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-ENCODING: [0xb7,0x8d,0xe8,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 8d e8 c4 <unknown>
+
+ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x15,0x95,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 95 c4 <unknown>
+
+ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x15,0xd5,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 d5 c4 <unknown>
+
+ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+// CHECK-INST: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+// CHECK-ENCODING: [0x00,0x00,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 a0 c4 <unknown>
+
+ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+// CHECK-INST: ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+// CHECK-ENCODING: [0x00,0x00,0xe0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 e0 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1sw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sw.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sw.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sw.s Thu Apr 26 01:19:53 2018
@@ -42,3 +42,39 @@ ld1sw { z23.d }, p3/z, [x13, x8, lsl
// CHECK-ENCODING: [0xb7,0x4d,0x88,0xa4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 4d 88 a4 <unknown>
+
+ld1sw { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1sw { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0x9f,0x5f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 5f c5 <unknown>
+
+ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-INST: ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-ENCODING: [0xb7,0x8d,0x68,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 8d 68 c5 <unknown>
+
+ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x15,0x15,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 15 c5 <unknown>
+
+ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x15,0x55,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 15 55 c5 <unknown>
+
+ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+// CHECK-INST: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+// CHECK-ENCODING: [0x00,0x00,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 20 c5 <unknown>
+
+ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+// CHECK-INST: ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+// CHECK-ENCODING: [0x00,0x00,0x60,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 60 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ld1w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1w.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1w.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1w.s Thu Apr 26 01:19:53 2018
@@ -72,3 +72,63 @@ ld1w { z23.d }, p3/z, [x13, x8, lsl #
// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 4d 68 a5 <unknown>
+
+ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x40,0x00,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 85 <unknown>
+
+ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x40,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 85 <unknown>
+
+ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
+// CHECK-INST: ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
+// CHECK-ENCODING: [0xff,0x5f,0x3f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 5f 3f 85 <unknown>
+
+ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
+// CHECK-INST: ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
+// CHECK-ENCODING: [0xff,0x5f,0x7f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 5f 7f 85 <unknown>
+
+ld1w { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ld1w { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xdf,0x5f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 5f c5 <unknown>
+
+ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-INST: ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-ENCODING: [0xb7,0xcd,0x68,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 cd 68 c5 <unknown>
+
+ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x55,0x15,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 15 c5 <unknown>
+
+ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x55,0x55,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 55 55 c5 <unknown>
+
+ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+// CHECK-INST: ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+// CHECK-ENCODING: [0x00,0x40,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 20 c5 <unknown>
+
+ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+// CHECK-INST: ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+// CHECK-ENCODING: [0x00,0x40,0x60,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 60 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1b.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1b.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1b.s Thu Apr 26 01:19:53 2018
@@ -72,3 +72,33 @@ ldff1b { z0.d }, p0/z, [x0, x0]
// CHECK-ENCODING: [0x00,0x60,0x60,0xa4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 60 a4 <unknown>
+
+ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x60,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 00 84 <unknown>
+
+ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x60,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 40 84 <unknown>
+
+ldff1b { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1b { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xff,0x5f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 5f c4 <unknown>
+
+ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x75,0x15,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 15 c4 <unknown>
+
+ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x75,0x55,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 55 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s Thu Apr 26 01:19:53 2018
@@ -30,22 +30,22 @@ ldff1d z4.d, p8/z, [x0]
// Invalid scalar + scalar addressing modes
ldff1d z0.d, p0/z, [x0, sp]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, sp]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1d z0.d, p0/z, [x0, x0, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, x0, lsl #1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1d z0.d, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1d z0.d, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1d.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1d.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1d.s Thu Apr 26 01:19:53 2018
@@ -24,3 +24,39 @@ ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x60,0xe0,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 e0 a5 <unknown>
+
+ldff1d { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1d { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xff,0xdf,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff df c5 <unknown>
+
+ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+// CHECK-INST: ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed e8 c5 <unknown>
+
+ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x75,0x95,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 95 c5 <unknown>
+
+ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x75,0xd5,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 d5 c5 <unknown>
+
+ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+// CHECK-INST: ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+// CHECK-ENCODING: [0x00,0x60,0xa0,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 a0 c5 <unknown>
+
+ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+// CHECK-INST: ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+// CHECK-ENCODING: [0x00,0x60,0xe0,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 e0 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1h.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1h.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1h.s Thu Apr 26 01:19:53 2018
@@ -60,3 +60,63 @@ ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x60,0xe0,0xa4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 e0 a4 <unknown>
+
+ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x60,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 80 84 <unknown>
+
+ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x60,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 c0 84 <unknown>
+
+ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+// CHECK-INST: ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+// CHECK-ENCODING: [0xff,0x7f,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7f bf 84 <unknown>
+
+ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+// CHECK-INST: ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+// CHECK-ENCODING: [0xff,0x7f,0xff,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7f ff 84 <unknown>
+
+ldff1h { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1h { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xff,0xdf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff df c4 <unknown>
+
+ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-INST: ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed e8 c4 <unknown>
+
+ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x75,0x95,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 95 c4 <unknown>
+
+ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x75,0xd5,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 d5 c4 <unknown>
+
+ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+// CHECK-INST: ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+// CHECK-ENCODING: [0x00,0x60,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 a0 c4 <unknown>
+
+ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+// CHECK-INST: ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+// CHECK-ENCODING: [0x00,0x60,0xe0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 e0 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sb.s Thu Apr 26 01:19:53 2018
@@ -60,3 +60,33 @@ ldff1sb { z0.d }, p0/z, [x0, x0]
// CHECK-ENCODING: [0x00,0x60,0x80,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 80 a5 <unknown>
+
+ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x20,0x00,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 00 84 <unknown>
+
+ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x20,0x40,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 40 84 <unknown>
+
+ldff1sb { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1sb { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xbf,0x5f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5f c4 <unknown>
+
+ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x35,0x15,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 15 c4 <unknown>
+
+ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x35,0x55,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 55 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s Thu Apr 26 01:19:53 2018
@@ -25,21 +25,21 @@ ldff1sh z4.d, p8/z, [x0]
// Invalid scalar + scalar addressing modes
ldff1sh z0.s, p0/z, [x0, sp]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, sp]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sh z0.s, p0/z, [x0, x0, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sh z0.s, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sh z0.s, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sh.s Thu Apr 26 01:19:53 2018
@@ -42,3 +42,63 @@ ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x60,0x00,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 00 a5 <unknown>
+
+ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x20,0x80,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 80 84 <unknown>
+
+ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x20,0xc0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 c0 84 <unknown>
+
+ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+// CHECK-INST: ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+// CHECK-ENCODING: [0xff,0x3f,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3f bf 84 <unknown>
+
+ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+// CHECK-INST: ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+// CHECK-ENCODING: [0xff,0x3f,0xff,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3f ff 84 <unknown>
+
+ldff1sh { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1sh { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xbf,0xdf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf df c4 <unknown>
+
+ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-INST: ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+// CHECK-ENCODING: [0xb7,0xad,0xe8,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ad e8 c4 <unknown>
+
+ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x35,0x95,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 95 c4 <unknown>
+
+ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x35,0xd5,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 d5 c4 <unknown>
+
+ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+// CHECK-INST: ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+// CHECK-ENCODING: [0x00,0x20,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 a0 c4 <unknown>
+
+ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+// CHECK-INST: ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+// CHECK-ENCODING: [0x00,0x20,0xe0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 e0 c4 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s Thu Apr 26 01:19:53 2018
@@ -20,21 +20,21 @@ ldff1sw z4.d, p8/z, [x0]
// Invalid scalar + scalar addressing modes
ldff1sw z0.d, p0/z, [x0, sp]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, sp]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sw z0.d, p0/z, [x0, x0, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sw z0.d, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1sw z0.d, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sw.s Thu Apr 26 01:19:53 2018
@@ -24,3 +24,39 @@ ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x60,0x80,0xa4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 80 a4 <unknown>
+
+ldff1sw { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1sw { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xbf,0x5f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5f c5 <unknown>
+
+ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-INST: ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-ENCODING: [0xb7,0xad,0x68,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ad 68 c5 <unknown>
+
+ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x35,0x15,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 15 c5 <unknown>
+
+ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x35,0x55,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 35 55 c5 <unknown>
+
+ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+// CHECK-INST: ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+// CHECK-ENCODING: [0x00,0x20,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 20 c5 <unknown>
+
+ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+// CHECK-INST: ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+// CHECK-ENCODING: [0x00,0x20,0x60,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 60 c5 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s Thu Apr 26 01:19:53 2018
@@ -30,21 +30,21 @@ ldff1w z4.d, p8/z, [x0]
// Invalid scalar + scalar addressing modes
ldff1w z0.s, p0/z, [x0, sp]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, sp]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1w z0.s, p0/z, [x0, x0, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, x0, lsl #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1w z0.s, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ldff1w z0.s, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/ldff1w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldff1w.s?rev=330928&r1=330927&r2=330928&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1w.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1w.s Thu Apr 26 01:19:53 2018
@@ -42,3 +42,63 @@ ldff1w { z0.d }, p0/z, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x60,0x60,0xa5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 60 60 a5 <unknown>
+
+ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-INST: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
+// CHECK-ENCODING: [0x00,0x60,0x00,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 00 85 <unknown>
+
+ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-INST: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
+// CHECK-ENCODING: [0x00,0x60,0x40,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 40 85 <unknown>
+
+ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
+// CHECK-INST: ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
+// CHECK-ENCODING: [0xff,0x7f,0x3f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7f 3f 85 <unknown>
+
+ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
+// CHECK-INST: ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
+// CHECK-ENCODING: [0xff,0x7f,0x7f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 7f 7f 85 <unknown>
+
+ldff1w { z31.d }, p7/z, [sp, z31.d]
+// CHECK-INST: ldff1w { z31.d }, p7/z, [sp, z31.d]
+// CHECK-ENCODING: [0xff,0xff,0x5f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 5f c5 <unknown>
+
+ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-INST: ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
+// CHECK-ENCODING: [0xb7,0xed,0x68,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 68 c5 <unknown>
+
+ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-INST: ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
+// CHECK-ENCODING: [0x55,0x75,0x15,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 15 c5 <unknown>
+
+ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-INST: ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
+// CHECK-ENCODING: [0x55,0x75,0x55,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 75 55 c5 <unknown>
+
+ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+// CHECK-INST: ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+// CHECK-ENCODING: [0x00,0x60,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 20 c5 <unknown>
+
+ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+// CHECK-INST: ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+// CHECK-ENCODING: [0x00,0x60,0x60,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 60 c5 <unknown>
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