[llvm] r330659 - [X86] Remove unnecessary BMI2 InstRW overrides.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 23 15:19:55 PDT 2018
Author: rksimon
Date: Mon Apr 23 15:19:55 2018
New Revision: 330659
URL: http://llvm.org/viewvc/llvm-project?rev=330659&view=rev
Log:
[X86] Remove unnecessary BMI2 InstRW overrides.
We have test coverage for these with resources-bmi2.s
Modified:
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330659&r1=330658&r2=330659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Apr 23 15:19:55 2018
@@ -726,16 +726,12 @@ def: InstRW<[HWWriteResGroup7], (instreg
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "RORX(32|64)ri",
"SAR(8|16|32|64)r1",
"SAR(8|16|32|64)ri",
- "SARX(32|64)rr",
"SHL(8|16|32|64)r1",
"SHL(8|16|32|64)ri",
- "SHLX(32|64)rr",
"SHR(8|16|32|64)r1",
- "SHR(8|16|32|64)ri",
- "SHRX(32|64)rr")>;
+ "SHR(8|16|32|64)ri")>;
def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
let Latency = 1;
@@ -956,11 +952,7 @@ def HWWriteResGroup15 : SchedWriteRes<[H
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8",
- "RORX(32|64)mi",
- "SARX(32|64)rm",
- "SHLX(32|64)rm",
- "SHRX(32|64)rm")>;
+def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>;
def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
let Latency = 6;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330659&r1=330658&r2=330659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Apr 23 15:19:55 2018
@@ -463,19 +463,15 @@ def: InstRW<[SKLWriteResGroup7], (instre
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "RORX(32|64)ri",
"SAR(8|16|32|64)r1",
"SAR(8|16|32|64)ri",
- "SARX(32|64)rr",
"SBB(16|32|64)ri",
"SBB(16|32|64)i",
"SBB(8|16|32|64)rr",
"SHL(8|16|32|64)r1",
"SHL(8|16|32|64)ri",
- "SHLX(32|64)rr",
"SHR(8|16|32|64)r1",
- "SHR(8|16|32|64)ri",
- "SHRX(32|64)rr")>;
+ "SHR(8|16|32|64)ri")>;
def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
let Latency = 1;
@@ -1185,11 +1181,7 @@ def SKLWriteResGroup74 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8",
- "RORX(32|64)mi",
- "SARX(32|64)rm",
- "SHLX(32|64)rm",
- "SHRX(32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[SKLWriteResGroup74, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
ADCX32rm, ADCX64rm,
ADOX32rm, ADOX64rm,
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330659&r1=330658&r2=330659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Apr 23 15:19:55 2018
@@ -768,19 +768,15 @@ def: InstRW<[SKXWriteResGroup7], (instre
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "RORX(32|64)ri",
"SAR(8|16|32|64)r1",
"SAR(8|16|32|64)ri",
- "SARX(32|64)rr",
"SBB(16|32|64)ri",
"SBB(16|32|64)i",
"SBB(8|16|32|64)rr",
"SHL(8|16|32|64)r1",
"SHL(8|16|32|64)ri",
- "SHLX(32|64)rr",
"SHR(8|16|32|64)r1",
- "SHR(8|16|32|64)ri",
- "SHRX(32|64)rr")>;
+ "SHR(8|16|32|64)ri")>;
def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
let Latency = 1;
@@ -2348,11 +2344,7 @@ def SKXWriteResGroup78 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8",
- "RORX(32|64)mi",
- "SARX(32|64)rm",
- "SHLX(32|64)rm",
- "SHRX(32|64)rm")>;
+def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[SKXWriteResGroup78, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
ADCX32rm, ADCX64rm,
ADOX32rm, ADOX64rm,
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