[PATCH] D45995: [DAGCombiner] Set the right SDLoc on a newly-created zextload

[Vedant Kumar via Phabricator via llvm-commits]

vsk created this revision.
vsk added reviewers: rnk, aprantl, ab, niravd.
Herald added a reviewer: javed.absar.

Setting the right SDLoc on a newly-created zextload fixes a line table
bug which resulted in non-linear stepping behavior.

Several backend tests contained CHECK lines which relied on the IROrder
inherited from the wrong SDLoc. This patch breaks that dependence where
feasbile and regenerates test cases where not.

rdar://33755881


https://reviews.llvm.org/D45995

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/arm64-aapcs.ll
  test/CodeGen/AArch64/arm64-ldp-cluster.ll
  test/CodeGen/ARM/vector-load.ll
  test/CodeGen/X86/avg.ll
  test/CodeGen/X86/dagcombine-cse.ll
  test/CodeGen/X86/fold-zext-trunc-dbginfo.ll
  test/CodeGen/X86/known-bits-vector.ll
  test/CodeGen/X86/legalize-shift-64.ll
  test/CodeGen/X86/load-combine.ll
  test/CodeGen/X86/mulx32.ll
  test/CodeGen/X86/promote-vec3.ll
  test/CodeGen/X86/widen_conv-3.ll
  test/CodeGen/X86/widen_conv-4.ll
  test/CodeGen/X86/win-smallparams.ll

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