[llvm] r330588 - [X86] Remove instregex matching from CLAC/STAC.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Apr 23 06:24:17 2018
New Revision: 330588

URL: http://llvm.org/viewvc/llvm-project?rev=330588&view=rev
Log:
[X86] Remove instregex matching from CLAC/STAC.

Note - noticed this as the STAC case as it was unintentionally matching against *STACK* pseudo instructions.

Modified:
    llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330588&r1=330587&r2=330588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Apr 23 06:24:17 2018
@@ -450,7 +450,7 @@ def SKLWriteResGroup7 : SchedWriteRes<[S
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO)>;
+def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
                                             "ADC(16|32|64)i",
                                             "ADC(8|16|32|64)rr",
@@ -464,7 +464,6 @@ def: InstRW<[SKLWriteResGroup7], (instre
                                             "BTR(16|32|64)rr",
                                             "BTS(16|32|64)ri8",
                                             "BTS(16|32|64)rr",
-                                            "CLAC",
                                             "RORX(32|64)ri",
                                             "SAR(8|16|32|64)r1",
                                             "SAR(8|16|32|64)ri",
@@ -477,8 +476,7 @@ def: InstRW<[SKLWriteResGroup7], (instre
                                             "SHLX(32|64)rr",
                                             "SHR(8|16|32|64)r1",
                                             "SHR(8|16|32|64)ri",
-                                            "SHRX(32|64)rr",
-                                            "STAC")>;
+                                            "SHRX(32|64)rr")>;
 
 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
   let Latency = 1;

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330588&r1=330587&r2=330588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Apr 23 06:24:17 2018
@@ -755,7 +755,7 @@ def SKXWriteResGroup7 : SchedWriteRes<[S
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO)>;
+def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri",
                                             "ADC(16|32|64)i",
                                             "ADC(8|16|32|64)rr",
@@ -769,7 +769,6 @@ def: InstRW<[SKXWriteResGroup7], (instre
                                             "BTR(16|32|64)rr",
                                             "BTS(16|32|64)ri8",
                                             "BTS(16|32|64)rr",
-                                            "CLAC",
                                             "RORX(32|64)ri",
                                             "SAR(8|16|32|64)r1",
                                             "SAR(8|16|32|64)ri",
@@ -782,8 +781,7 @@ def: InstRW<[SKXWriteResGroup7], (instre
                                             "SHLX(32|64)rr",
                                             "SHR(8|16|32|64)r1",
                                             "SHR(8|16|32|64)ri",
-                                            "SHRX(32|64)rr",
-                                            "STAC")>;
+                                            "SHRX(32|64)rr")>;
 
 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
   let Latency = 1;