[PATCH] D45821: [AArch64] improve code generation of vectors smaller than 64 bit

[Sebastian Pop via Phabricator via llvm-commits]

sebpop added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll:8
+; CHECK:      str x30, [sp, #-16]!
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: adrp x8, q
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This change doesn't look good.


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Comment at: llvm/test/CodeGen/AArch64/complex-fp-to-int.ll:40
+; CHECK: fcvtzs w
+; CHECK: fcvtzs w
 
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I need to investigate why these are scalarized.


https://reviews.llvm.org/D45821