[llvm] r330333 - [Hexagon] Generate code for vector bswap intrinsics

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Apr 19 07:46:44 2018
New Revision: 330333

URL: http://llvm.org/viewvc/llvm-project?rev=330333&view=rev
Log:
[Hexagon] Generate code for vector bswap intrinsics

Added:
    llvm/trunk/test/CodeGen/Hexagon/autohvx/bswap.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td?rev=330333&r1=330332&r2=330333&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td Thu Apr 19 07:46:44 2018
@@ -357,6 +357,11 @@ let Predicates = [UseHVX] in {
            (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
   def: Pat<(VecI16 (trunc HWI32:$Vss)),
            (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
+
+  def: Pat<(VecI16 (bswap HVI16:$Vs)),
+           (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
+  def: Pat<(VecI32 (bswap HVI32:$Vs)),
+           (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>;
 }
 
 class HvxSel_pat<InstHexagon MI, PatFrag RegPred>

Added: llvm/trunk/test/CodeGen/Hexagon/autohvx/bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/bswap.ll?rev=330333&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/bswap.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/bswap.ll Thu Apr 19 07:46:44 2018
@@ -0,0 +1,45 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: test_00
+; CHECK: [[R00:r[0-9]+]] = ##16843009
+; CHECK: [[V00:v[0-9]+]] = vsplat([[R00]])
+; CHECK: v0 = vdelta(v0,[[V00]])
+define <32 x i16> @test_00(<32 x i16> %a0) #0 {
+  %v0 = call <32 x i16> @llvm.bswap.v32i16(<32 x i16> %a0)
+  ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: test_01
+; CHECK: [[R01:r[0-9]+]] = ##50529027
+; CHECK: [[V01:v[0-9]+]] = vsplat([[R01]])
+; CHECK: v0 = vdelta(v0,[[V01]])
+define <16 x i32> @test_01(<16 x i32> %a0) #0 {
+  %v0 = call <16 x i32> @llvm.bswap.v16i32(<16 x i32> %a0)
+  ret <16 x i32> %v0
+}
+
+; CHECK-LABEL: test_10
+; CHECK: [[R10:r[0-9]+]] = ##16843009
+; CHECK: [[V10:v[0-9]+]] = vsplat([[R10]])
+; CHECK: v0 = vdelta(v0,[[V10]])
+define <64 x i16> @test_10(<64 x i16> %a0) #1 {
+  %v0 = call <64 x i16> @llvm.bswap.v64i16(<64 x i16> %a0)
+  ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: test_11
+; CHECK: [[R11:r[0-9]+]] = ##50529027
+; CHECK: [[V11:v[0-9]+]] = vsplat([[R11]])
+; CHECK: v0 = vdelta(v0,[[V11]])
+define <32 x i32> @test_11(<32 x i32> %a0) #1 {
+  %v0 = call <32 x i32> @llvm.bswap.v32i32(<32 x i32> %a0)
+  ret <32 x i32> %v0
+}
+
+declare <32 x i16> @llvm.bswap.v32i16(<32 x i16>) #0
+declare <16 x i32> @llvm.bswap.v16i32(<16 x i32>) #0
+declare <64 x i16> @llvm.bswap.v64i16(<64 x i16>) #1
+declare <32 x i32> @llvm.bswap.v32i32(<32 x i32>) #1
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }