[llvm] r330332 - [X86][BtVer2] Remove SSE4A EXTRQ/EXTRQI InstRW overrides.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 19 07:38:36 PDT 2018
Author: rksimon
Date: Thu Apr 19 07:38:36 2018
New Revision: 330332
URL: http://llvm.org/viewvc/llvm-project?rev=330332&view=rev
Log:
[X86][BtVer2] Remove SSE4A EXTRQ/EXTRQI InstRW overrides.
These are already handled identically by WriteALU.
Modified:
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=330332&r1=330331&r2=330332&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Thu Apr 19 07:38:36 2018
@@ -488,10 +488,6 @@ def : InstRW<[JWriteDPPDLd], (instrs DPP
// SSE4A instructions.
////////////////////////////////////////////////////////////////////////////////
-def JWriteEXTRQ: SchedWriteRes<[JFPU01, JVALU]> {
-}
-def : InstRW<[JWriteEXTRQ], (instrs EXTRQ, EXTRQI)>;
-
def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> {
let Latency = 2;
let ResourceCycles = [1, 4];
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