[llvm] r330204 - [X86] Add separate scheduling class for PSADBW instruction.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 17 12:35:20 PDT 2018
Author: ctopper
Date: Tue Apr 17 12:35:19 2018
New Revision: 330204
URL: http://llvm.org/viewvc/llvm-project?rev=330204&view=rev
Log:
[X86] Add separate scheduling class for PSADBW instruction.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86Schedule.td
llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
llvm/trunk/test/CodeGen/X86/avx2-schedule.ll
llvm/trunk/test/CodeGen/X86/mmx-schedule.ll
llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Apr 17 12:35:19 2018
@@ -10076,7 +10076,7 @@ multiclass avx512_psadbw_packed_all<bits
}
defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
- WriteMPSAD, HasBWI>, EVEX_4V, VEX_WIG;
+ WritePSADBW, HasBWI>, EVEX_4V, VEX_WIG;
// Transforms to swizzle an immediate to enable better matching when
// memory operand isn't in the right place.
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Tue Apr 17 12:35:19 2018
@@ -384,7 +384,7 @@ defm MMX_PMAXSW : MMXI_binop_rm_int<0xE
WriteVecALU, 1>;
defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
- WriteVecIMul, 1>;
+ WritePSADBW, 1>;
}
defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Apr 17 12:35:19 2018
@@ -3370,15 +3370,15 @@ defm PMADDWD : PDI_binop_rm2<0xF5, "pmad
let Predicates = [HasAVX, NoVLX_Or_NoBWI] in
defm VPSADBW : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v2i64, v16i8, VR128,
- loadv2i64, i128mem, WriteVecALU, 0>,
+ loadv2i64, i128mem, WritePSADBW, 0>,
VEX_4V, VEX_WIG;
let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in
defm VPSADBWY : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v4i64, v32i8, VR256,
- loadv4i64, i256mem, WriteVecALU, 0>,
+ loadv4i64, i256mem, WritePSADBW, 0>,
VEX_4V, VEX_L, VEX_WIG;
let Constraints = "$src1 = $dst" in
defm PSADBW : PDI_binop_rm2<0xF6, "psadbw", X86psadbw, v2i64, v16i8, VR128,
- memopv2i64, i128mem, WriteVecALU>;
+ memopv2i64, i128mem, WritePSADBW>;
//===---------------------------------------------------------------------===//
// SSE2 - Packed Integer Logical Instructions
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Tue Apr 17 12:35:19 2018
@@ -185,6 +185,7 @@ defm : BWWriteResPair<WriteVarShuffle, [
defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
+defm : BWWriteResPair<WritePSADBW, [BWPort0], 5>; // Vector PSADBW.
// Vector bitwise operations.
// These are often used on both floating point and integer vectors.
@@ -1097,7 +1098,6 @@ def: InstRW<[BWWriteResGroup47], (instre
"MMX_PMULHWirr",
"MMX_PMULLWirr",
"MMX_PMULUDQirr",
- "MMX_PSADBWirr",
"MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
@@ -1111,7 +1111,6 @@ def: InstRW<[BWWriteResGroup47], (instre
"(V?)PMULHW(Y?)rr",
"(V?)PMULLW(Y?)rr",
"(V?)PMULUDQ(Y?)rr",
- "(V?)PSADBW(Y?)rr",
"(V?)RCPPSr",
"(V?)RCPSSr",
"(V?)RSQRTPSr",
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Tue Apr 17 12:35:19 2018
@@ -185,6 +185,7 @@ defm : HWWriteResPair<WriteVarShuffle256
defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2]>;
defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 2, [2, 1]>;
defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 6, [1, 2]>;
+defm : HWWriteResPair<WritePSADBW, [HWPort0], 5>;
// String instructions.
@@ -2257,7 +2258,6 @@ def: InstRW<[HWWriteResGroup89], (instre
"MMX_PMULHWirr",
"MMX_PMULLWirr",
"MMX_PMULUDQirr",
- "MMX_PSADBWirr",
"MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
@@ -2271,7 +2271,6 @@ def: InstRW<[HWWriteResGroup89], (instre
"(V?)PMULHW(Y?)rr",
"(V?)PMULLW(Y?)rr",
"(V?)PMULUDQ(Y?)rr",
- "(V?)PSADBW(Y?)rr",
"(V?)RCPPSr",
"(V?)RCPSSr",
"(V?)RSQRTPSr",
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Tue Apr 17 12:35:19 2018
@@ -169,6 +169,7 @@ defm : SBWriteResPair<WriteVarShuffle,
defm : SBWriteResPair<WriteBlend, [SBPort15], 1>;
defm : SBWriteResPair<WriteVarBlend, [SBPort1, SBPort5], 2>;
defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 5, [1,2], 3>;
+defm : SBWriteResPair<WritePSADBW, [SBPort0], 5>;
////////////////////////////////////////////////////////////////////////////////
// Horizontal add/sub instructions.
@@ -616,9 +617,7 @@ def: InstRW<[SBWriteResGroup20], (instre
"MMX_PMULHUWirr",
"MMX_PMULHWirr",
"MMX_PMULLWirr",
- "MMX_PMULUDQirr",
- "MMX_PSADBWirr",
- "(V?)PSADBWrr")>;
+ "MMX_PMULUDQirr")>;
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
let Latency = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Tue Apr 17 12:35:19 2018
@@ -182,6 +182,7 @@ defm : SKLWriteResPair<WriteVarShuffle,
defm : SKLWriteResPair<WriteBlend, [SKLPort15], 1>; // Vector blends.
defm : SKLWriteResPair<WriteVarBlend, [SKLPort5], 2, [2]>; // Vector variable blends.
defm : SKLWriteResPair<WriteMPSAD, [SKLPort0, SKLPort5], 6, [1, 2]>; // Vector MPSAD.
+defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3>; // Vector PSADBW.
// Vector bitwise operations.
// These are often used on both floating point and integer vectors.
@@ -858,7 +859,6 @@ def SKLWriteResGroup30 : SchedWriteRes<[
def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0",
"ADD_FST0r",
"ADD_FrST0",
- "MMX_PSADBWirr",
"SUBR_FPrST0",
"SUBR_FST0r",
"SUBR_FrST0",
@@ -891,8 +891,7 @@ def: InstRW<[SKLWriteResGroup30], (instr
"VPMOVZXBWYrr",
"VPMOVZXDQYrr",
"VPMOVZXWDYrr",
- "VPMOVZXWQYrr",
- "(V?)PSADBW(Y?)rr")>;
+ "VPMOVZXWQYrr")>;
def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let Latency = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Tue Apr 17 12:35:19 2018
@@ -182,6 +182,7 @@ defm : SKXWriteResPair<WriteVarShuffle,
defm : SKXWriteResPair<WriteBlend, [SKXPort15], 1>; // Vector blends.
defm : SKXWriteResPair<WriteVarBlend, [SKXPort5], 2, [2]>; // Vector variable blends.
defm : SKXWriteResPair<WriteMPSAD, [SKXPort0, SKXPort5], 6, [1, 2]>; // Vector MPSAD.
+defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3>; // Vector PSADBW.
// Vector bitwise operations.
// These are often used on both floating point and integer vectors.
@@ -1683,9 +1684,7 @@ def: InstRW<[SKXWriteResGroup32], (instr
"KUNPCKBWrr",
"KUNPCKDQrr",
"KUNPCKWDrr",
- "MMX_PSADBWirr",
"PCMPGTQrr",
- "PSADBWrr",
"SUBR_FPrST0",
"SUBR_FST0r",
"SUBR_FrST0",
@@ -1901,11 +1900,7 @@ def: InstRW<[SKXWriteResGroup32], (instr
"VPMOVZXWQZ128rr",
"VPMOVZXWQZ256rr",
"VPMOVZXWQZrr",
- "VPSADBWYrr",
- "VPSADBWZ128rr",
- "VPSADBWZ256rr",
- "VPSADBWZrr",
- "VPSADBWrr",
+ "VPSADBWZrr", // TODO: 512-bit ops require ports 0/1 to be joined.
"VPTESTMBZ128rr",
"VPTESTMBZ256rr",
"VPTESTMBZrr",
Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Tue Apr 17 12:35:19 2018
@@ -111,6 +111,7 @@ defm WriteShuffle : X86SchedWritePair;
defm WriteVarShuffle : X86SchedWritePair; // Vector variable shuffles.
defm WriteBlend : X86SchedWritePair; // Vector blends.
defm WriteVarBlend : X86SchedWritePair; // Vector variable blends.
+defm WritePSADBW : X86SchedWritePair; // Vector PSADBW.
defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
// Vector bitwise operations.
Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Tue Apr 17 12:35:19 2018
@@ -240,6 +240,7 @@ defm : AtomWriteResPair<WriteVecShift,
defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
defm : AtomWriteResPair<WritePMULLD, [AtomPort01], [AtomPort0], 1, 1>;
defm : AtomWriteResPair<WriteMPSAD, [AtomPort01], [AtomPort0], 1, 1>;
+defm : AtomWriteResPair<WritePSADBW, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>;
defm : AtomWriteResPair<WriteVarShuffle, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>;
defm : AtomWriteResPair<WriteBlend, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Tue Apr 17 12:35:19 2018
@@ -370,6 +370,7 @@ defm : JWriteResFpuPair<WriteVecShift,
defm : JWriteResFpuPair<WriteVecIMul, [JFPU0, JVIMUL], 2>;
defm : JWriteResFpuPair<WritePMULLD, [JFPU0, JFPU01, JVIMUL, JVALU], 4, [2, 1, 2, 1], 3>;
defm : JWriteResFpuPair<WriteMPSAD, [JFPU0, JVIMUL], 3, [1, 2]>;
+defm : JWriteResFpuPair<WritePSADBW, [JFPU01, JVALU], 2>;
defm : JWriteResFpuPair<WriteShuffle, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVarShuffle, [JFPU01, JVALU], 2, [1, 4], 3>;
defm : JWriteResFpuPair<WriteBlend, [JFPU01, JVALU], 1>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Tue Apr 17 12:35:19 2018
@@ -155,6 +155,7 @@ defm : SLMWriteResPair<WriteShuffle, [S
defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>;
+defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>;
////////////////////////////////////////////////////////////////////////////////
// Horizontal add/sub instructions.
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Tue Apr 17 12:35:19 2018
@@ -226,6 +226,7 @@ defm : ZnWriteResFpuPair<WriteVarShuffle
defm : ZnWriteResFpuPair<WriteBlend, [ZnFPU01], 1>;
defm : ZnWriteResFpuPair<WriteShuffle256, [ZnFPU], 2>;
defm : ZnWriteResFpuPair<WriteVarShuffle256, [ZnFPU], 2>;
+defm : ZnWriteResFpuPair<WritePSADBW, [ZnFPU0], 3>;
// Vector Shift Operations
defm : ZnWriteResFpuPair<WriteVarVecShift, [ZnFPU12], 1>;
Modified: llvm/trunk/test/CodeGen/X86/avx2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-schedule.ll?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-schedule.ll Tue Apr 17 12:35:19 2018
@@ -5087,8 +5087,8 @@ define <4 x i64> @test_por(<4 x i64> %a0
define <4 x i64> @test_psadbw(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> *%a2) {
; GENERIC-LABEL: test_psadbw:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; GENERIC-NEXT: vpsadbw (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; GENERIC-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
+; GENERIC-NEXT: vpsadbw (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_psadbw:
@@ -5117,8 +5117,8 @@ define <4 x i64> @test_psadbw(<32 x i8>
;
; ZNVER1-LABEL: test_psadbw:
; ZNVER1: # %bb.0:
-; ZNVER1-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 # sched: [1:0.25]
-; ZNVER1-NEXT: vpsadbw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; ZNVER1-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
+; ZNVER1-NEXT: vpsadbw (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %a0, <32 x i8> %a1)
%2 = bitcast <4 x i64> %1 to <32 x i8>
Modified: llvm/trunk/test/CodeGen/X86/mmx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-schedule.ll?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mmx-schedule.ll Tue Apr 17 12:35:19 2018
@@ -4637,15 +4637,15 @@ define i64 @test_psadbw(x86_mmx %a0, x86
;
; BTVER2-LABEL: test_psadbw:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: psadbw %mm1, %mm0 # sched: [2:1.00]
+; BTVER2-NEXT: psadbw %mm1, %mm0 # sched: [2:0.50]
; BTVER2-NEXT: psadbw (%rdi), %mm0 # sched: [7:1.00]
; BTVER2-NEXT: movq %mm0, %rax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_psadbw:
; ZNVER1: # %bb.0:
-; ZNVER1-NEXT: psadbw %mm1, %mm0 # sched: [4:1.00]
-; ZNVER1-NEXT: psadbw (%rdi), %mm0 # sched: [11:1.00]
+; ZNVER1-NEXT: psadbw %mm1, %mm0 # sched: [3:1.00]
+; ZNVER1-NEXT: psadbw (%rdi), %mm0 # sched: [10:1.00]
; ZNVER1-NEXT: movq %mm0, %rax # sched: [2:1.00]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx %a0, x86_mmx %a1)
Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Tue Apr 17 12:35:19 2018
@@ -10332,18 +10332,14 @@ define <2 x i64> @test_psadbw(<16 x i8>
;
; ATOM-LABEL: test_psadbw:
; ATOM: # %bb.0:
-; ATOM-NEXT: psadbw %xmm1, %xmm0 # sched: [1:0.50]
-; ATOM-NEXT: psadbw (%rdi), %xmm0 # sched: [1:1.00]
-; ATOM-NEXT: nop # sched: [1:0.50]
-; ATOM-NEXT: nop # sched: [1:0.50]
-; ATOM-NEXT: nop # sched: [1:0.50]
-; ATOM-NEXT: nop # sched: [1:0.50]
+; ATOM-NEXT: psadbw %xmm1, %xmm0 # sched: [5:5.00]
+; ATOM-NEXT: psadbw (%rdi), %xmm0 # sched: [5:5.00]
; ATOM-NEXT: retq # sched: [79:39.50]
;
; SLM-LABEL: test_psadbw:
; SLM: # %bb.0:
-; SLM-NEXT: psadbw %xmm1, %xmm0 # sched: [1:0.50]
-; SLM-NEXT: psadbw (%rdi), %xmm0 # sched: [4:1.00]
+; SLM-NEXT: psadbw %xmm1, %xmm0 # sched: [4:1.00]
+; SLM-NEXT: psadbw (%rdi), %xmm0 # sched: [7:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-SSE-LABEL: test_psadbw:
@@ -10408,26 +10404,26 @@ define <2 x i64> @test_psadbw(<16 x i8>
;
; BTVER2-SSE-LABEL: test_psadbw:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: psadbw %xmm1, %xmm0 # sched: [1:0.50]
-; BTVER2-SSE-NEXT: psadbw (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-SSE-NEXT: psadbw %xmm1, %xmm0 # sched: [2:0.50]
+; BTVER2-SSE-NEXT: psadbw (%rdi), %xmm0 # sched: [7:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_psadbw:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; BTVER2-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
+; BTVER2-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_psadbw:
; ZNVER1-SSE: # %bb.0:
-; ZNVER1-SSE-NEXT: psadbw %xmm1, %xmm0 # sched: [1:0.25]
-; ZNVER1-SSE-NEXT: psadbw (%rdi), %xmm0 # sched: [8:0.50]
+; ZNVER1-SSE-NEXT: psadbw %xmm1, %xmm0 # sched: [3:1.00]
+; ZNVER1-SSE-NEXT: psadbw (%rdi), %xmm0 # sched: [10:1.00]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
; ZNVER1-LABEL: test_psadbw:
; ZNVER1: # %bb.0:
-; ZNVER1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [1:0.25]
-; ZNVER1-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [8:0.50]
+; ZNVER1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; ZNVER1-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1)
%2 = bitcast <2 x i64> %1 to <16 x i8>
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s?rev=330204&r1=330203&r2=330204&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s Tue Apr 17 12:35:19 2018
@@ -1526,8 +1526,8 @@ vzeroupper
# CHECK-NEXT: 1 7 1.00 * vpmuludq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpor %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 1 6 1.00 * vpor (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 1 0.50 vpsadbw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1 6 1.00 * vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 7 1.00 * vpsadbw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 2 2.00 vpshufb %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 3 7 2.00 * vpshufb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpshufd $1, %xmm0, %xmm2
More information about the llvm-commits
mailing list