[llvm] r330203 - [X86] Remove unnecessary InstRW overrides. Add somes FIXMEs/TODOs.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 17 12:35:15 PDT 2018
Author: ctopper
Date: Tue Apr 17 12:35:14 2018
New Revision: 330203
URL: http://llvm.org/viewvc/llvm-project?rev=330203&view=rev
Log:
[X86] Remove unnecessary InstRW overrides. Add somes FIXMEs/TODOs.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330203&r1=330202&r2=330203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Tue Apr 17 12:35:14 2018
@@ -478,10 +478,6 @@ def: InstRW<[BWWriteResGroup6], (instreg
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
- "JMP_1",
- "JMP_4",
"RORX(32|64)ri",
"SAR(8|16|32|64)r1",
"SAR(8|16|32|64)ri",
@@ -614,9 +610,9 @@ def BWWriteResGroup9 : SchedWriteRes<[BW
def: InstRW<[BWWriteResGroup9], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[BWWriteResGroup9], (instregex "CLC",
"CMC",
- "LAHF",
+ "LAHF", // TODO: This doesnt match Agner's data
"NOOP",
- "SAHF",
+ "SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
"SLDT64m",
@@ -1138,7 +1134,6 @@ def BWWriteResGroup49 : SchedWriteRes<[B
def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm",
"MMX_MOVD64to64rm",
"MMX_MOVQ64rm",
- "MOV(16|32|64)rm",
"MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330203&r1=330202&r2=330203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Tue Apr 17 12:35:14 2018
@@ -619,7 +619,6 @@ def HWWriteResGroup0_2 : SchedWriteRes<[
def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVD64rm",
"MMX_MOVD64to64rm",
"MMX_MOVQ64rm",
- "MOV(8|16|32|64)rm",
"MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
@@ -831,10 +830,6 @@ def: InstRW<[HWWriteResGroup7], (instreg
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
- "JMP_1",
- "JMP_4",
"RORX(32|64)ri",
"SAR(8|16|32|64)r1",
"SAR(8|16|32|64)ri",
@@ -964,9 +959,9 @@ def HWWriteResGroup10 : SchedWriteRes<[H
def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[HWWriteResGroup10], (instregex "CLC",
"CMC",
- "LAHF",
+ "LAHF", // TODO: This doesn't match Agner's data
"NOOP",
- "SAHF",
+ "SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
"SLDT64m",
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330203&r1=330202&r2=330203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Tue Apr 17 12:35:14 2018
@@ -319,31 +319,20 @@ def SBWriteResGroup2 : SchedWriteRes<[SB
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>;
+def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs.
def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP",
"FFREE",
"FINCSTP",
"FNOP",
"INSERTPSrr",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
- "JMP(16|32|64)r",
- "JMP_1",
- "JMP_4",
"LD_Frr",
"RETQ",
"ST_FPrr",
"ST_Frr",
- "(V?)ANDNPD(Y?)rr",
- "(V?)ANDNPS(Y?)rr",
- "(V?)ANDPD(Y?)rr",
- "(V?)ANDPS(Y?)rr",
"VEXTRACTF128rr",
"VINSERTF128rr",
"VINSERTPSrr",
"(V?)MOV64toPQIrr",
- "(V?)MOVAPD(Y?)rr",
- "(V?)MOVAPS(Y?)rr",
"(V?)MOVDDUP(Y?)rr",
"(V?)MOVDI2PDIrr",
"(V?)MOVHLPSrr",
@@ -354,19 +343,11 @@ def: InstRW<[SBWriteResGroup2], (instreg
"(V?)MOVSSrr",
"(V?)MOVUPD(Y?)rr",
"(V?)MOVUPS(Y?)rr",
- "(V?)ORPD(Y?)rr",
- "(V?)ORPS(Y?)rr",
"VPERM2F128rr",
"VPERMILPD(Y?)ri",
"VPERMILPS(Y?)ri",
"(V?)SHUFPD(Y?)rri",
- "(V?)SHUFPS(Y?)rri",
- "(V?)UNPCKHPD(Y?)rr",
- "(V?)UNPCKHPS(Y?)rr",
- "(V?)UNPCKLPD(Y?)rr",
- "(V?)UNPCKLPS(Y?)rr",
- "(V?)XORPD(Y?)rr",
- "(V?)XORPS(Y?)rr")>;
+ "(V?)SHUFPS(Y?)rri")>;
def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
let Latency = 1;
@@ -391,14 +372,6 @@ def: InstRW<[SBWriteResGroup4], (instreg
"BTS(16|32|64)rr",
"LAHF",
"SAHF",
- "SAR(8|16|32|64)ri",
- "SAR(8|16|32|64)r1",
- "SHL(8|16|32|64)ri",
- "SHL(8|16|32|64)r1",
- "SHR(8|16|32|64)ri",
- "SHR(8|16|32|64)r1",
- "(V?)BLENDPD(Y?)rri",
- "(V?)BLENDPS(Y?)rri",
"VMOVDQA(Y?)rr",
"VMOVDQU(Y?)rr")>;
@@ -433,7 +406,6 @@ def: InstRW<[SBWriteResGroup5], (instreg
"(V?)PALIGNRrri",
"(V?)PAVGBrr",
"(V?)PAVGWrr",
- "(V?)PBLENDWrri",
"(V?)PCMPEQBrr",
"(V?)PCMPEQDrr",
"(V?)PCMPEQQrr",
@@ -495,15 +467,10 @@ def SBWriteResGroup6 : SchedWriteRes<[SB
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup6], (instrs CBW, CWDE, CDQE)>;
-def: InstRW<[SBWriteResGroup6], (instregex "CMC",
- "MMX_MOVD64from64rr",
+def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr",
"MMX_MOVQ2DQrr",
- "MOV(8|16|32|64)rr",
- "MOV(8|16|32|64)ri",
- "MOVDQArr",
- "MOVDQUrr",
- "STC",
+ "MOVDQArr", //TODO: Why are these separated from their VEX equivalent
+ "MOVDQUrr", // TODO: Why are these separated from their VEX equivalent
"(V?)MOVPQI2QIrr",
"(V?)MOVZPQILo2PQIrr",
"(V?)PANDNrr",
@@ -651,14 +618,6 @@ def: InstRW<[SBWriteResGroup20], (instre
"MMX_PMULLWirr",
"MMX_PMULUDQirr",
"MMX_PSADBWirr",
- "(V?)PMADDUBSWrr",
- "(V?)PMADDWDrr",
- "(V?)PMULDQrr",
- "(V?)PMULHRSWrr",
- "(V?)PMULHUWrr",
- "(V?)PMULHWrr",
- "(V?)PMULLWrr",
- "(V?)PMULUDQrr",
"(V?)PSADBWrr")>;
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
@@ -666,14 +625,12 @@ def SBWriteResGroup21 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup21], (instrs MUL8r, IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0",
"ADD_FST0r",
"ADD_FrST0",
"MMX_CVTPI2PSirr",
"MMX_CVTPS2PIirr",
"MMX_CVTTPS2PIirr",
- "POPCNT(16|32|64)rr",
"PUSHFS64",
"SUBR_FPrST0",
"SUBR_FST0r",
@@ -681,23 +638,13 @@ def: InstRW<[SBWriteResGroup21], (instre
"SUB_FPrST0",
"SUB_FST0r",
"SUB_FrST0",
- "(V?)ADDPD(Y?)rr",
- "(V?)ADDPS(Y?)rr",
- "(V?)ADDSDrr",
- "(V?)ADDSSrr",
- "(V?)ADDSUBPD(Y?)rr",
- "(V?)ADDSUBPS(Y?)rr",
"(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
"(V?)CVTTPS2DQ(Y?)rr",
"(V?)ROUNDPD(Y?)r",
"(V?)ROUNDPS(Y?)r",
"(V?)ROUNDSDr",
- "(V?)ROUNDSSr",
- "(V?)SUBPD(Y?)rr",
- "(V?)SUBPS(Y?)rr",
- "(V?)SUBSDrr",
- "(V?)SUBSSrr")>;
+ "(V?)ROUNDSSr")>;
def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> {
let Latency = 3;
@@ -867,8 +814,7 @@ def SBWriteResGroup31 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup31], (instregex "MOV(8|16|32|64)rm",
- "MOVSX(16|32|64)rm16",
+def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
@@ -1026,28 +972,21 @@ def: InstRW<[SBWriteResGroup48], (instre
"VBROADCASTSSrm",
"(V?)LDDQU(Y?)rm",
"(V?)MOV64toPQIrm",
- "(V?)MOVAPDrm",
- "(V?)MOVAPSrm",
"(V?)MOVDDUPrm",
"(V?)MOVDI2PDIrm",
- "(V?)MOVDQArm",
- "(V?)MOVDQUrm",
"(V?)MOVNTDQArm",
"(V?)MOVQI2PQIrm",
"(V?)MOVSDrm",
"(V?)MOVSHDUPrm",
"(V?)MOVSLDUPrm",
- "(V?)MOVSSrm",
- "(V?)MOVUPDrm",
- "(V?)MOVUPSrm")>;
+ "(V?)MOVSSrm")>;
def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup49], (instregex "JMP(16|32|64)m",
- "MOV16sm")>;
+def: InstRW<[SBWriteResGroup49], (instregex "MOV16sm")>;
def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 6;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330203&r1=330202&r2=330203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Tue Apr 17 12:35:14 2018
@@ -543,10 +543,6 @@ def: InstRW<[SKLWriteResGroup7], (instre
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
"CLAC",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
- "JMP_1",
- "JMP_4",
"RORX(32|64)ri",
"SAR(8|16|32|64)r1",
"SAR(8|16|32|64)ri",
@@ -618,9 +614,9 @@ def SKLWriteResGroup10 : SchedWriteRes<[
def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SKLWriteResGroup10], (instregex "CLC",
"CMC",
- "LAHF",
+ "LAHF", // TODO: This doesn't match Agner's data
"NOOP",
- "SAHF",
+ "SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
"SLDT64m",
@@ -1175,7 +1171,6 @@ def SKLWriteResGroup58 : SchedWriteRes<[
def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64rm",
"MMX_MOVD64to64rm",
"MMX_MOVQ64rm",
- "MOV(8|16|32|64)rm",
"MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330203&r1=330202&r2=330203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Tue Apr 17 12:35:14 2018
@@ -1006,10 +1006,6 @@ def: InstRW<[SKXWriteResGroup7], (instre
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
"CLAC",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
- "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
- "JMP_1",
- "JMP_4",
"RORX(32|64)ri",
"SAR(8|16|32|64)r1",
"SAR(8|16|32|64)ri",
@@ -1265,9 +1261,9 @@ def SKXWriteResGroup10 : SchedWriteRes<[
def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SKXWriteResGroup10], (instregex "CLC",
"CMC",
- "LAHF",
+ "LAHF", // TODO: This doesn't match Agner's data
"NOOP",
- "SAHF",
+ "SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
"SLDT64m",
@@ -2528,7 +2524,6 @@ def SKXWriteResGroup58 : SchedWriteRes<[
def: InstRW<[SKXWriteResGroup58], (instregex "MMX_MOVD64rm",
"MMX_MOVD64to64rm",
"MMX_MOVQ64rm",
- "MOV(8|16|32|64)rm",
"MOV64toPQIrm",
"MOVDDUPrm",
"MOVDI2PDIrm",
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