[PATCH] D45640: [MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs()

[Roman Tereshin via Phabricator via llvm-commits]

rtereshin created this revision.
rtereshin added reviewers: dblaikie, grosbach, aditya_nandakumar, aemerson, volkan, manmanren, stoklund.
Herald added subscribers: kristof.beyls, javed.absar.

Apparently, MachineInstr class definition as well as pretty much all of
the machine passes assume that the only kind of MachineInstr's operands
that is variadic for variadic opcodes is explicit non-definitions.

In particular, this assumption is made by MachineInstr::defs(), uses(),
and explicit_uses() methods, as well as by MachineCSE pass.

The assumption is incorrect judging from at least TableGen backend
implementation, that recognizes variable_ops in OutOperandList, and the
very existence of G_UNMERGE_VALUES generic opcode, or ARM load multiple
instructions, all of which have variadic defs.

In particular, MachineCSE pass breaks MIR with CSE'able G_UNMERGE_VALUES
instructions in it.

This commit implements MachineInstr::getNumExplicitDefs() similar to
pre-existing MachineInstr::getNumExplicitOperands(), fixes
MachineInstr::defs(), uses(), and explicit_uses(), and fixes MachineCSE
pass.

As the issue addressed seems to affect only machine passes that could be
ran mid-GlobalISel pipeline at the moment, the other passes aren't fixed
by this commit, like MachineLICM: that could be done on per-pass basis
when (if ever) they get adopted for GlobalISel.


Repository:
  rL LLVM

https://reviews.llvm.org/D45640

Files:
  include/llvm/CodeGen/MachineInstr.h
  lib/CodeGen/MachineCSE.cpp
  lib/CodeGen/MachineInstr.cpp
  test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir

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