[PATCH] D45585: [DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon, efriedma.

We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets.

Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue.

This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here.

There are couple tests where the instruction counts went up. I need to look closer at those.


https://reviews.llvm.org/D45585

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/3addr-16bit.ll
  test/CodeGen/X86/avx512-mask-op.ll
  test/CodeGen/X86/fixup-bw-copy.ll
  test/CodeGen/X86/iabs.ll
  test/CodeGen/X86/ins_subreg_coalesce-1.ll
  test/CodeGen/X86/mul-constant-i16.ll
  test/CodeGen/X86/popcnt.ll
  test/CodeGen/X86/pr32345.ll
  test/CodeGen/X86/pr32420.ll
  test/CodeGen/X86/pr34137.ll
  test/CodeGen/X86/promote-i16.ll
  test/CodeGen/X86/reduce-trunc-shl.ll

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