[llvm] r329877 - [RISCV] Codegen support for RV32D floating point comparison operations
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 11 22:50:06 PDT 2018
Author: asb
Date: Wed Apr 11 22:50:06 2018
New Revision: 329877
URL: http://llvm.org/viewvc/llvm-project?rev=329877&view=rev
Log:
[RISCV] Codegen support for RV32D floating point comparison operations
Also add double-prevoius-failure.ll which captures a test case that at one
point triggered a compiler crash, while developing calling convention support
for f64 on RV32D with soft-float ABI.
Added:
llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/double-previous-failure.ll
llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll
Modified:
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=329877&r1=329876&r2=329877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Wed Apr 11 22:50:06 2018
@@ -108,13 +108,15 @@ RISCVTargetLowering::RISCVTargetLowering
setOperationAction(ISD::CTLZ, XLenVT, Expand);
setOperationAction(ISD::CTPOP, XLenVT, Expand);
+ ISD::CondCode FPCCToExtend[] = {
+ ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETO, ISD::SETUEQ,
+ ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE,
+ ISD::SETGT, ISD::SETGE, ISD::SETNE};
+
if (Subtarget.hasStdExtF()) {
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
- for (auto CC :
- {ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETO, ISD::SETUEQ,
- ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE,
- ISD::SETGT, ISD::SETGE, ISD::SETNE})
+ for (auto CC : FPCCToExtend)
setCondCodeAction(CC, MVT::f32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
setOperationAction(ISD::SELECT, MVT::f32, Custom);
@@ -124,6 +126,11 @@ RISCVTargetLowering::RISCVTargetLowering
if (Subtarget.hasStdExtD()) {
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
+ for (auto CC : FPCCToExtend)
+ setCondCodeAction(CC, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT, MVT::f64, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f64, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
}
@@ -473,6 +480,7 @@ RISCVTargetLowering::EmitInstrWithCustom
llvm_unreachable("Unexpected instr type to insert");
case RISCV::Select_GPR_Using_CC_GPR:
case RISCV::Select_FPR32_Using_CC_GPR:
+ case RISCV::Select_FPR64_Using_CC_GPR:
break;
case RISCV::BuildPairF64Pseudo:
return emitBuildPairF64Pseudo(MI, BB);
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp?rev=329877&r1=329876&r2=329877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp Wed Apr 11 22:50:06 2018
@@ -43,14 +43,18 @@ void RISCVInstrInfo::copyPhysReg(Machine
return;
}
- if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
- BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_S), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc))
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
+ // FPR->FPR copies
+ unsigned Opc;
+ if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
+ Opc = RISCV::FSGNJ_S;
+ else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
+ Opc = RISCV::FSGNJ_D;
+ else
+ llvm_unreachable("Impossible reg-to-reg copy");
- llvm_unreachable("Impossible reg-to-reg copy");
+ BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(SrcReg, getKillRegState(KillSrc));
}
void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td?rev=329877&r1=329876&r2=329877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td Wed Apr 11 22:50:06 2018
@@ -239,10 +239,24 @@ def : PatFpr64Fpr64<fmaxnum, FMAX_D>;
/// Setcc
+def : PatFpr64Fpr64<seteq, FEQ_D>;
def : PatFpr64Fpr64<setoeq, FEQ_D>;
+def : PatFpr64Fpr64<setlt, FLT_D>;
def : PatFpr64Fpr64<setolt, FLT_D>;
+def : PatFpr64Fpr64<setle, FLE_D>;
def : PatFpr64Fpr64<setole, FLE_D>;
+// Define pattern expansions for setcc operations which aren't directly
+// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
+// Legalizer.
+
+def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
+ (SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
+ (FEQ_D FPR64:$rs2, FPR64:$rs2)),
+ 1)>;
+
+def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>;
+
/// Loads
defm : LdPat<load, FLD>;
Added: llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll?rev=329877&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll Wed Apr 11 22:50:06 2018
@@ -0,0 +1,534 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IFD %s
+
+declare void @abort()
+declare void @exit(i32)
+
+define void @br_fcmp_false(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_false:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: addi a0, zero, 1
+; RV32IFD-NEXT: bnez a0, .LBB0_2
+; RV32IFD-NEXT: # %bb.1: # %if.then
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB0_2: # %if.else
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp false double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.then:
+ ret void
+if.else:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_oeq(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_oeq:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB1_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB1_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp oeq double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+; TODO: generated code quality for this is very poor due to
+; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
+; expansion.
+define void @br_fcmp_oeq_alt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_oeq_alt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: beqz a0, .LBB2_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB2_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp oeq double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.then:
+ tail call void @abort()
+ unreachable
+if.else:
+ ret void
+}
+
+define void @br_fcmp_ogt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_ogt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB3_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB3_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp ogt double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_oge(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_oge:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB4_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB4_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp oge double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_olt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_olt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB5_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB5_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp olt double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ole(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_ole:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB6_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB6_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp ole double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+; TODO: feq.s+sltiu+bne -> feq.s+beq
+define void @br_fcmp_one(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_one:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: feq.d a1, ft0, ft1
+; RV32IFD-NEXT: not a1, a1
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: bnez a0, .LBB7_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB7_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp one double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ord(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_ord:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB8_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB8_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp ord double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ueq(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_ueq:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: feq.d a2, ft1, ft1
+; RV32IFD-NEXT: and a1, a2, a1
+; RV32IFD-NEXT: seqz a1, a1
+; RV32IFD-NEXT: or a0, a0, a1
+; RV32IFD-NEXT: bnez a0, .LBB9_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB9_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp ueq double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ugt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_ugt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB10_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB10_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp ugt double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_uge(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_uge:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB11_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB11_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp uge double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ult(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_ult:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB12_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB12_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp ult double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ule(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_ule:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB13_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB13_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp ule double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_une(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_une:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB14_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB14_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp une double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_uno(double %a, double %b) nounwind {
+; TODO: sltiu+bne -> beq
+; RV32IFD-LABEL: br_fcmp_uno:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: sw a2, 0(sp)
+; RV32IFD-NEXT: sw a3, 4(sp)
+; RV32IFD-NEXT: fld ft1, 0(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: bnez a0, .LBB15_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB15_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp uno double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_true(double %a, double %b) nounwind {
+; RV32IFD-LABEL: br_fcmp_true:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: addi a0, zero, 1
+; RV32IFD-NEXT: bnez a0, .LBB16_2
+; RV32IFD-NEXT: # %bb.1: # %if.else
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+; RV32IFD-NEXT: .LBB16_2: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+ %1 = fcmp true double %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
Added: llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll?rev=329877&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll Wed Apr 11 22:50:06 2018
@@ -0,0 +1,299 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IFD %s
+
+define i32 @fcmp_false(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_false:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: mv a0, zero
+; RV32IFD-NEXT: ret
+ %1 = fcmp false double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_oeq(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_oeq:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp oeq double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ogt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_ogt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ogt double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_oge(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_oge:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp oge double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_olt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_olt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp olt double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ole(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_ole:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ole double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_one(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_one:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: feq.d a1, ft0, ft1
+; RV32IFD-NEXT: not a1, a1
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp one double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ord(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_ord:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ord double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ueq(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_ueq:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: feq.d a2, ft1, ft1
+; RV32IFD-NEXT: and a1, a2, a1
+; RV32IFD-NEXT: seqz a1, a1
+; RV32IFD-NEXT: or a0, a0, a1
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ueq double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ugt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_ugt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ugt double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_uge(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_uge:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp uge double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ult(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_ult:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ult double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ule(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_ule:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ule double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_une(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_une:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp une double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_uno(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_uno:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp uno double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_true(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fcmp_true:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi a0, zero, 1
+; RV32IFD-NEXT: ret
+ %1 = fcmp true double %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
Added: llvm/trunk/test/CodeGen/RISCV/double-previous-failure.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-previous-failure.ll?rev=329877&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-previous-failure.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/double-previous-failure.ll Wed Apr 11 22:50:06 2018
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IFD %s
+
+define double @test(double %a) nounwind {
+; RV32IFD-LABEL: test:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: ret
+ ret double %a
+}
+
+; This previously failed complaining of multiple vreg defs due to an ABI
+; lowering issue.
+
+define i32 @main() nounwind {
+; RV32IFD-LABEL: main:
+; RV32IFD: # %bb.0: # %entry
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: lui a0, %hi(test)
+; RV32IFD-NEXT: addi a2, a0, %lo(test)
+; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
+; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
+; RV32IFD-NEXT: fld ft0, 0(a0)
+; RV32IFD-NEXT: fsd ft0, 0(sp)
+; RV32IFD-NEXT: lw a0, 0(sp)
+; RV32IFD-NEXT: lw a1, 4(sp)
+; RV32IFD-NEXT: jalr a2
+; RV32IFD-NEXT: sw a0, 0(sp)
+; RV32IFD-NEXT: sw a1, 4(sp)
+; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
+; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_1)
+; RV32IFD-NEXT: fld ft1, 0(a0)
+; RV32IFD-NEXT: flt.d a0, ft0, ft1
+; RV32IFD-NEXT: bnez a0, .LBB1_3
+; RV32IFD-NEXT: # %bb.1: # %entry
+; RV32IFD-NEXT: lui a0, %hi(.LCPI1_2)
+; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_2)
+; RV32IFD-NEXT: fld ft1, 0(a0)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: beqz a0, .LBB1_3
+; RV32IFD-NEXT: # %bb.2: # %if.end
+; RV32IFD-NEXT: lui a0, %hi(exit)
+; RV32IFD-NEXT: addi a1, a0, %lo(exit)
+; RV32IFD-NEXT: mv a0, zero
+; RV32IFD-NEXT: jalr a1
+; RV32IFD-NEXT: .LBB1_3: # %if.then
+; RV32IFD-NEXT: lui a0, %hi(abort)
+; RV32IFD-NEXT: addi a0, a0, %lo(abort)
+; RV32IFD-NEXT: jalr a0
+entry:
+ %call = call double @test(double 2.000000e+00)
+ %cmp = fcmp olt double %call, 2.400000e-01
+ %cmp2 = fcmp ogt double %call, 2.600000e-01
+ %or.cond = or i1 %cmp, %cmp2
+ br i1 %or.cond, label %if.then, label %if.end
+
+if.then:
+ call void @abort()
+ unreachable
+
+if.end:
+ call void @exit(i32 0)
+ unreachable
+}
+
+declare void @abort()
+
+declare void @exit(i32)
Added: llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll?rev=329877&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll Wed Apr 11 22:50:06 2018
@@ -0,0 +1,423 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IFD %s
+
+define double @select_fcmp_false(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_false:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: mv a0, a2
+; RV32IFD-NEXT: mv a1, a3
+; RV32IFD-NEXT: ret
+ %1 = fcmp false double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_oeq(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_oeq:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB1_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft1, ft0
+; RV32IFD-NEXT: .LBB1_2:
+; RV32IFD-NEXT: fsd ft1, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp oeq double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_ogt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_ogt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB2_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft0, ft1
+; RV32IFD-NEXT: .LBB2_2:
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ogt double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_oge(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_oge:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB3_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft0, ft1
+; RV32IFD-NEXT: .LBB3_2:
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp oge double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_olt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_olt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB4_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft1, ft0
+; RV32IFD-NEXT: .LBB4_2:
+; RV32IFD-NEXT: fsd ft1, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp olt double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_ole(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_ole:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB5_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft1, ft0
+; RV32IFD-NEXT: .LBB5_2:
+; RV32IFD-NEXT: fsd ft1, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ole double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_one(double %a, double %b) nounwind {
+; TODO: feq.s+sltiu+bne sequence could be optimised
+; RV32IFD-LABEL: select_fcmp_one:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: feq.d a1, ft0, ft1
+; RV32IFD-NEXT: not a1, a1
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: bnez a0, .LBB6_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft0, ft1
+; RV32IFD-NEXT: .LBB6_2:
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp one double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_ord(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_ord:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB7_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft0, ft1
+; RV32IFD-NEXT: .LBB7_2:
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ord double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_ueq(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_ueq:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: feq.d a1, ft0, ft1
+; RV32IFD-NEXT: or a0, a1, a0
+; RV32IFD-NEXT: bnez a0, .LBB8_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft0, ft1
+; RV32IFD-NEXT: .LBB8_2:
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ueq double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_ugt(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_ugt:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB9_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft1, ft0
+; RV32IFD-NEXT: .LBB9_2:
+; RV32IFD-NEXT: fsd ft1, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ugt double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_uge(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_uge:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB10_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft1, ft0
+; RV32IFD-NEXT: .LBB10_2:
+; RV32IFD-NEXT: fsd ft1, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp uge double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_ult(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_ult:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: fle.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB11_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft0, ft1
+; RV32IFD-NEXT: .LBB11_2:
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ult double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_ule(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_ule:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: flt.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB12_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft0, ft1
+; RV32IFD-NEXT: .LBB12_2:
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp ule double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_une(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_une:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: bnez a0, .LBB13_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft1, ft0
+; RV32IFD-NEXT: .LBB13_2:
+; RV32IFD-NEXT: fsd ft1, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp une double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_uno(double %a, double %b) nounwind {
+; TODO: sltiu+bne could be optimized
+; RV32IFD-LABEL: select_fcmp_uno:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft1
+; RV32IFD-NEXT: feq.d a1, ft0, ft0
+; RV32IFD-NEXT: and a0, a1, a0
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: bnez a0, .LBB14_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: fmv.d ft0, ft1
+; RV32IFD-NEXT: .LBB14_2:
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp uno double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+define double @select_fcmp_true(double %a, double %b) nounwind {
+; RV32IFD-LABEL: select_fcmp_true:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: ret
+ %1 = fcmp true double %a, %b
+ %2 = select i1 %1, double %a, double %b
+ ret double %2
+}
+
+; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
+define i32 @i32_select_fcmp_oeq(double %a, double %b, i32 %c, i32 %d) nounwind {
+; RV32IFD-LABEL: i32_select_fcmp_oeq:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: feq.d a0, ft1, ft0
+; RV32IFD-NEXT: bnez a0, .LBB16_2
+; RV32IFD-NEXT: # %bb.1:
+; RV32IFD-NEXT: mv a4, a5
+; RV32IFD-NEXT: .LBB16_2:
+; RV32IFD-NEXT: mv a0, a4
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fcmp oeq double %a, %b
+ %2 = select i1 %1, i32 %c, i32 %d
+ ret i32 %2
+}
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