[llvm] r329876 - [RISCV] Codegen support for RV32D floating point conversion operations
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 11 22:47:15 PDT 2018
Author: asb
Date: Wed Apr 11 22:47:15 2018
New Revision: 329876
URL: http://llvm.org/viewvc/llvm-project?rev=329876&view=rev
Log:
[RISCV] Codegen support for RV32D floating point conversion operations
This also includes support and a test for truncating stores, which are now
possible thanks to the fpround pattern.
Added:
llvm/trunk/test/CodeGen/RISCV/double-convert.ll
Modified:
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/trunk/test/CodeGen/RISCV/double-mem.ll
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=329876&r1=329875&r2=329876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Wed Apr 11 22:47:15 2018
@@ -125,6 +125,7 @@ RISCVTargetLowering::RISCVTargetLowering
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
}
setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td?rev=329876&r1=329875&r2=329876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td Wed Apr 11 22:47:15 2018
@@ -199,6 +199,20 @@ class PatFpr64Fpr64DynFrm<SDPatternOpera
let Predicates = [HasStdExtD] in {
+/// Float conversion operations
+
+// f64 -> f32, f32 -> f64
+def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>;
+def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
+
+// FP->[u]int. Round-to-zero must be used
+def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_W_D FPR64:$rs1, 0b001)>;
+def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_WU_D FPR64:$rs1, 0b001)>;
+
+// [u]int->fp
+def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_W GPR:$rs1)>;
+def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_WU GPR:$rs1)>;
+
/// Float arithmetic operations
def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
Added: llvm/trunk/test/CodeGen/RISCV/double-convert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-convert.ll?rev=329876&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-convert.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/double-convert.ll Wed Apr 11 22:47:15 2018
@@ -0,0 +1,89 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IFD %s
+
+define float @fcvt_s_d(double %a) nounwind {
+; RV32IFD-LABEL: fcvt_s_d:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: fcvt.s.d ft0, ft0
+; RV32IFD-NEXT: fmv.x.w a0, ft0
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fptrunc double %a to float
+ ret float %1
+}
+
+define double @fcvt_d_s(float %a) nounwind {
+; RV32IFD-LABEL: fcvt_d_s:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: fmv.w.x ft0, a0
+; RV32IFD-NEXT: fcvt.d.s ft0, ft0
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fpext float %a to double
+ ret double %1
+}
+
+define i32 @fcvt_w_d(double %a) nounwind {
+; RV32IFD-LABEL: fcvt_w_d:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fptosi double %a to i32
+ ret i32 %1
+}
+
+define i32 @fcvt_wu_d(double %a) nounwind {
+; RV32IFD-LABEL: fcvt_wu_d:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fptoui double %a to i32
+ ret i32 %1
+}
+
+define double @fcvt_d_w(i32 %a) nounwind {
+; RV32IFD-LABEL: fcvt_d_w:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: fcvt.d.w ft0, a0
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = sitofp i32 %a to double
+ ret double %1
+}
+
+define double @fcvt_d_wu(i32 %a) nounwind {
+; RV32IFD-LABEL: fcvt_d_wu:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: fcvt.d.wu ft0, a0
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = uitofp i32 %a to double
+ ret double %1
+}
Modified: llvm/trunk/test/CodeGen/RISCV/double-mem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-mem.ll?rev=329876&r1=329875&r2=329876&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-mem.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/double-mem.ll Wed Apr 11 22:47:15 2018
@@ -170,3 +170,20 @@ define void @fsd_stack(double %a, double
call void @notdead(i8* %3)
ret void
}
+
+; Test selection of store<ST4[%a], trunc to f32>, ..
+define void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
+; RV32IFD-LABEL: fsd_trunc:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a1, 8(sp)
+; RV32IFD-NEXT: sw a2, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: fcvt.s.d ft0, ft0
+; RV32IFD-NEXT: fsw ft0, 0(a0)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = fptrunc double %b to float
+ store float %1, float* %a, align 4
+ ret void
+}
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