[PATCH] D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86InstrAVX512.td:2771
 let Predicates = [HasBWI] in {
+  let isMoveReg = 0 in
   defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
----------------
Why is it disabled for this class and KMOVB above?


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Comment at: lib/Target/X86/X86InstrAVX512.td:3243
   let hasSideEffects = 0 in {
   def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
                     !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
----------------
This should be tagged I think.


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Comment at: lib/Target/X86/X86InstrAVX512.td:3323
                                   SDPatternOperator SelectOprr = vselect> {
-  let Predicates = [prd] in
   defm Z : avx512_load<opc, OpcodeStr, SSE_MOVU, _.info512, _.info512.LdFrag,
----------------
Why was this line deleted?


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Comment at: lib/Target/X86/X86InstrAVX512.td:3343
   let hasSideEffects = 0 in {
   def rr_REV  : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
                          OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
----------------
This should be tagged I think.


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Comment at: lib/Target/X86/X86InstrInfo.td:1616
     SchedRW = [WriteMove] in {
 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
                    "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>,
----------------
What about these?


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Comment at: lib/Target/X86/X86InstrMMX.td:295
 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
 def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
                         "movq\t{$src, $dst|$dst, $src}", [],
----------------
Why isn't MMX_MOVQ64rr_REV tagged?


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Comment at: lib/Target/X86/X86InstrSSE.td:650
 let hasSideEffects = 0 in
   def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
               !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
----------------
Shouldn't this be move reg?


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Comment at: lib/Target/X86/X86InstrSSE.td:743
     SchedRW = [WriteFShuffle] in {
+  let isMoveReg = 1 in
   def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
----------------
Why is this only on VMOVAPSrr_REV and not the 3 following instructions?


https://reviews.llvm.org/D45204