[llvm] r328542 - [Pipeliner] Use latency to compute RecMII
Galina Kistanova via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 10 15:30:03 PDT 2018
Hello Krzysztof,
> +++ llvm/trunk/test/CodeGen/Hexagon/sdr-reg-profit.ll Mon Mar 26
09:33:16 2018
> @@ -1,3 +1,5 @@
> +; XFAIL: *
> +; This requires further patches.
Please do not use XFAIL to disable a flaky test, as it could randomly pass
as well.
I have made this test unsupported instead in r329763.
Thanks
Galina
On Mon, Mar 26, 2018 at 9:33 AM, Krzysztof Parzyszek via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: kparzysz
> Date: Mon Mar 26 09:33:16 2018
> New Revision: 328542
>
> URL: http://llvm.org/viewvc/llvm-project?rev=328542&view=rev
> Log:
> [Pipeliner] Use latency to compute RecMII
>
> The patch contains severals changes needed to pipeline an example
> that was transformed so that a Phi with a subreg is converted to
> copies.
>
> The pipeliner wasn't working for a couple of reasons.
> - The RecMII was 3 instead of 2 due to the extra copies.
> - Copy instructions contained a latency of 1.
> - The node order algorithm was not choosing the best "bottom"
> node, which caused an instruction to be scheduled that had a
> predecessor and successor already scheduled.
> - Updated the Hexagon Machine Scheduler to check if the node is
> latency bound when adding the cost for a 0-latency dependence.
>
> The RecMII was 3 because the computation looks at the number of
> nodes in the recurrence. The extra copy is an extra node but
> it shouldn't increase the latency. The new RecMII computation
> looks at the latency of the instructions in the recurrence. We
> changed the latency of the dependence of a copy to 0. The latency
> computation for the copy also checks the use of the copy (similar
> to a reg_sequence).
>
> The node order algorithm was not choosing the last instruction
> in the recurrence for a bottom up traversal. This was when the
> last instruction is a copy. A check was added when choosing the
> instruction to check for NodeNum if the maxASAP is the same. This
> means that the scheduler will not end up with another node in
> the recurrence that has both a predecessor and successor already
> scheduled.
>
> The cost computation in Hexagon Machine Scheduler adds cost when
> an instruction can be packetized with a zero-latency instruction.
> We should only do this if the schedule is latency bound.
>
> Patch by Brendon Cahoon.
>
> Modified:
> llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
> llvm/trunk/test/CodeGen/Hexagon/sdr-reg-profit.ll
> llvm/trunk/test/CodeGen/Hexagon/swp-phi-ref.ll
>
> Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/
> CodeGen/MachinePipeliner.cpp?rev=328542&r1=328541&r2=328542&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Mon Mar 26 09:33:16 2018
> @@ -515,6 +515,8 @@ public:
> }
> }
>
> + unsigned getLatency() { return Latency; }
> +
> void clear() {
> Nodes.clear();
> RecMII = 0;
> @@ -1432,7 +1434,7 @@ unsigned SwingSchedulerDAG::calculateRec
> if (Nodes.empty())
> continue;
>
> - unsigned Delay = Nodes.size() - 1;
> + unsigned Delay = Nodes.getLatency();
> unsigned Distance = 1;
>
> // ii = ceil(delay / distance)
> @@ -2095,7 +2097,8 @@ void SwingSchedulerDAG::computeNodeOrder
> // Find the node with the highest ASAP.
> SUnit *maxASAP = nullptr;
> for (SUnit *SU : Nodes) {
> - if (maxASAP == nullptr || getASAP(SU) >= getASAP(maxASAP))
> + if (maxASAP == nullptr || getASAP(SU) > getASAP(maxASAP) ||
> + (getASAP(SU) == getASAP(maxASAP) && SU->NodeNum >
> maxASAP->NodeNum))
> maxASAP = SU;
> }
> R.insert(maxASAP);
> @@ -2106,7 +2109,7 @@ void SwingSchedulerDAG::computeNodeOrder
> while (!R.empty()) {
> if (Order == TopDown) {
> // Choose the node with the maximum height. If more than one,
> choose
> - // the node with the maximum ZeroLatencyHeight. If still more
> than one,
> + // the node wiTH the maximum ZeroLatencyHeight. If still more
> than one,
> // choose the node with the lowest MOV.
> while (!R.empty()) {
> SUnit *maxHeight = nullptr;
> @@ -3721,7 +3724,7 @@ void SMSchedule::computeStart(SUnit *SU,
> !SU->isPred(I))
> *MinLateStart = std::min(*MinLateStart, cycle);
> }
> - for (unsigned i = 0, e = (unsigned)SU->Succs.size(); i != e; ++i)
> + for (unsigned i = 0, e = (unsigned)SU->Succs.size(); i != e; ++i) {
> if (SU->Succs[i].getSUnit() == I) {
> const SDep &Dep = SU->Succs[i];
> if (!DAG->isBackedge(SU, Dep)) {
> @@ -3738,6 +3741,7 @@ void SMSchedule::computeStart(SUnit *SU,
> *MaxEarlyStart = std::max(*MaxEarlyStart, EarlyStart);
> }
> }
> + }
> }
> }
> }
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> Hexagon/HexagonInstrInfo.cpp?rev=328542&r1=328541&r2=328542&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Mon Mar 26
> 09:33:16 2018
> @@ -3952,9 +3952,9 @@ int HexagonInstrInfo::getOperandLatency(
> const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
>
> // Get DefIdx and UseIdx for super registers.
> - MachineOperand DefMO = DefMI.getOperand(DefIdx);
> + const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
>
> - if (HRI.isPhysicalRegister(DefMO.getReg())) {
> + if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) {
> if (DefMO.isImplicit()) {
> for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid();
> ++SR) {
> int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false,
> &HRI);
> @@ -3965,7 +3965,7 @@ int HexagonInstrInfo::getOperandLatency(
> }
> }
>
> - MachineOperand UseMO = UseMI.getOperand(UseIdx);
> + const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
> if (UseMO.isImplicit()) {
> for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid();
> ++SR) {
> int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> Hexagon/HexagonSubtarget.cpp?rev=328542&r1=328541&r2=328542&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Mon Mar 26
> 09:33:16 2018
> @@ -353,22 +353,27 @@ void HexagonSubtarget::adjustSchedDepend
> if (!hasV60TOps())
> return;
>
> - // If it's a REG_SEQUENCE, use its destination instruction to determine
> + // Set the latency for a copy to zero since we hope that is will get
> removed.
> + if (DstInst->isCopy())
> + Dep.setLatency(0);
> +
> + // If it's a REG_SEQUENCE/COPY, use its destination instruction to
> determine
> // the correct latency.
> - if (DstInst->isRegSequence() && Dst->NumSuccs == 1) {
> - unsigned RSeqReg = DstInst->getOperand(0).getReg();
> - MachineInstr *RSeqDst = Dst->Succs[0].getSUnit()->getInstr();
> + if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs ==
> 1) {
> + unsigned DReg = DstInst->getOperand(0).getReg();
> + MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr();
> unsigned UseIdx = -1;
> - for (unsigned OpNum = 0; OpNum < RSeqDst->getNumOperands(); OpNum++) {
> - const MachineOperand &MO = RSeqDst->getOperand(OpNum);
> - if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() ==
> RSeqReg) {
> + for (unsigned OpNum = 0; OpNum < DDst->getNumOperands(); OpNum++) {
> + const MachineOperand &MO = DDst->getOperand(OpNum);
> + if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg)
> {
> UseIdx = OpNum;
> break;
> }
> }
> - unsigned RSeqLatency = (InstrInfo.getOperandLatency(&InstrItins,
> *SrcInst,
> - 0, *RSeqDst,
> UseIdx));
> - Dep.setLatency(RSeqLatency);
> + int DLatency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst,
> + 0, *DDst, UseIdx));
> + DLatency = std::max(DLatency, 0);
> + Dep.setLatency((unsigned)DLatency);
> }
>
> // Try to schedule uses near definitions to generate .cur.
> @@ -448,8 +453,7 @@ void HexagonSubtarget::restoreLatency(SU
>
> // For some instructions (ex: COPY), we might end up with < 0
> latency
> // as they don't have any Itinerary class associated with them.
> - if (Latency <= 0)
> - Latency = 1;
> + Latency = std::max(Latency, 0);
>
> I.setLatency(Latency);
> updateLatency(*SrcI, *DstI, I);
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/sdr-reg-profit.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/Hexagon/sdr-reg-profit.ll?rev=328542&r1=328541&r2=328542&view=diff
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/Hexagon/sdr-reg-profit.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/sdr-reg-profit.ll Mon Mar 26 09:33:16
> 2018
> @@ -1,3 +1,5 @@
> +; XFAIL: *
> +; This requires further patches.
> ; RUN: llc -march=hexagon < %s | FileCheck %s
> ;
> ; Split all andp/orp instructions (by boosting the profitability of their
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/swp-phi-ref.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/Hexagon/swp-phi-ref.ll?rev=328542&r1=328541&r2=328542&view=diff
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/Hexagon/swp-phi-ref.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/swp-phi-ref.ll Mon Mar 26 09:33:16
> 2018
> @@ -8,9 +8,10 @@
> ; correct value. We need to do this even if we haven't generated the
> ; kernel code for the other Phi yet.
>
> -; CHECK: [[REG0:(v[0-9]+)]] = [[REG1:(v[0-9]+)]]
> +; CHECK: v[[REG0:[0-9]+]] = v[[REG1:[0-9]+]]
> ; CHECK: loop0
> -; CHECK: [[REG0]] = [[REG1]]
> +; Check for copy REG0 = REG1 (via vcombine):
> +; CHECK: v{{[0-9]+}}:[[REG0]] = vcombine(v{{[0-9]+}},v[[REG1]])
> ; CHECK: endloop0
>
> ; Function Attrs: nounwind
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180410/bd488238/attachment.html>
More information about the llvm-commits
mailing list