<div dir="ltr">Hello Krzysztof,<div><br></div><div>>
<span style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">+++ llvm/trunk/test/CodeGen/</span><span style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">Hexago<wbr>n/sdr-reg-profit.ll Mon Mar 26 09:33:16 2018</span><br style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial"><span style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">> @@ -1,3 +1,5 @@</span><br style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial"><span style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">> +; XFAIL: *</span><br style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial"><span style="color:rgb(34,34,34);font-family:arial,sans-serif;font-size:12.8px;font-style:normal;font-variant-ligatures:normal;font-variant-caps:normal;font-weight:400;letter-spacing:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline">> +; This requires further patches.</span>
</div><div><br></div><div>Please do not use XFAIL to disable a flaky test, as it could randomly pass as well.</div><div></div><div>I have made this test unsupported instead in <span style="font-size:12.8px">r329763</span>.<br><br></div><div>Thanks<br><br></div><div>Galina<br><br><br><br></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Mar 26, 2018 at 9:33 AM, Krzysztof Parzyszek via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: kparzysz<br>
Date: Mon Mar 26 09:33:16 2018<br>
New Revision: 328542<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=328542&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=328542&view=rev</a><br>
Log:<br>
[Pipeliner] Use latency to compute RecMII<br>
<br>
The patch contains severals changes needed to pipeline an example<br>
that was transformed so that a Phi with a subreg is converted to<br>
copies.<br>
<br>
The pipeliner wasn't working for a couple of reasons.<br>
- The RecMII was 3 instead of 2 due to the extra copies.<br>
- Copy instructions contained a latency of 1.<br>
- The node order algorithm was not choosing the best "bottom"<br>
node, which caused an instruction to be scheduled that had a<br>
predecessor and successor already scheduled.<br>
- Updated the Hexagon Machine Scheduler to check if the node is<br>
latency bound when adding the cost for a 0-latency dependence.<br>
<br>
The RecMII was 3 because the computation looks at the number of<br>
nodes in the recurrence. The extra copy is an extra node but<br>
it shouldn't increase the latency. The new RecMII computation<br>
looks at the latency of the instructions in the recurrence. We<br>
changed the latency of the dependence of a copy to 0. The latency<br>
computation for the copy also checks the use of the copy (similar<br>
to a reg_sequence).<br>
<br>
The node order algorithm was not choosing the last instruction<br>
in the recurrence for a bottom up traversal. This was when the<br>
last instruction is a copy. A check was added when choosing the<br>
instruction to check for NodeNum if the maxASAP is the same. This<br>
means that the scheduler will not end up with another node in<br>
the recurrence that has both a predecessor and successor already<br>
scheduled.<br>
<br>
The cost computation in Hexagon Machine Scheduler adds cost when<br>
an instruction can be packetized with a zero-latency instruction.<br>
We should only do this if the schedule is latency bound.<br>
<br>
Patch by Brendon Cahoon.<br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/<wbr>MachinePipeliner.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>HexagonSubtarget.cpp<br>
llvm/trunk/test/CodeGen/<wbr>Hexagon/sdr-reg-profit.ll<br>
llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-phi-ref.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>MachinePipeliner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=328542&r1=328541&r2=328542&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/MachinePipeliner.cpp?<wbr>rev=328542&r1=328541&r2=<wbr>328542&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>MachinePipeliner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>MachinePipeliner.cpp Mon Mar 26 09:33:16 2018<br>
@@ -515,6 +515,8 @@ public:<br>
}<br>
}<br>
<br>
+ unsigned getLatency() { return Latency; }<br>
+<br>
void clear() {<br>
Nodes.clear();<br>
RecMII = 0;<br>
@@ -1432,7 +1434,7 @@ unsigned SwingSchedulerDAG::<wbr>calculateRec<br>
if (Nodes.empty())<br>
continue;<br>
<br>
- unsigned Delay = Nodes.size() - 1;<br>
+ unsigned Delay = Nodes.getLatency();<br>
unsigned Distance = 1;<br>
<br>
// ii = ceil(delay / distance)<br>
@@ -2095,7 +2097,8 @@ void SwingSchedulerDAG::<wbr>computeNodeOrder<br>
// Find the node with the highest ASAP.<br>
SUnit *maxASAP = nullptr;<br>
for (SUnit *SU : Nodes) {<br>
- if (maxASAP == nullptr || getASAP(SU) >= getASAP(maxASAP))<br>
+ if (maxASAP == nullptr || getASAP(SU) > getASAP(maxASAP) ||<br>
+ (getASAP(SU) == getASAP(maxASAP) && SU->NodeNum > maxASAP->NodeNum))<br>
maxASAP = SU;<br>
}<br>
R.insert(maxASAP);<br>
@@ -2106,7 +2109,7 @@ void SwingSchedulerDAG::<wbr>computeNodeOrder<br>
while (!R.empty()) {<br>
if (Order == TopDown) {<br>
// Choose the node with the maximum height. If more than one, choose<br>
- // the node with the maximum ZeroLatencyHeight. If still more than one,<br>
+ // the node wiTH the maximum ZeroLatencyHeight. If still more than one,<br>
// choose the node with the lowest MOV.<br>
while (!R.empty()) {<br>
SUnit *maxHeight = nullptr;<br>
@@ -3721,7 +3724,7 @@ void SMSchedule::computeStart(SUnit *SU,<br>
!SU->isPred(I))<br>
*MinLateStart = std::min(*MinLateStart, cycle);<br>
}<br>
- for (unsigned i = 0, e = (unsigned)SU->Succs.size(); i != e; ++i)<br>
+ for (unsigned i = 0, e = (unsigned)SU->Succs.size(); i != e; ++i) {<br>
if (SU->Succs[i].getSUnit() == I) {<br>
const SDep &Dep = SU->Succs[i];<br>
if (!DAG->isBackedge(SU, Dep)) {<br>
@@ -3738,6 +3741,7 @@ void SMSchedule::computeStart(SUnit *SU,<br>
*MaxEarlyStart = std::max(*MaxEarlyStart, EarlyStart);<br>
}<br>
}<br>
+ }<br>
}<br>
}<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=328542&r1=328541&r2=328542&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Hexagon/HexagonInstrInfo.cpp?<wbr>rev=328542&r1=328541&r2=<wbr>328542&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrInfo.cpp Mon Mar 26 09:33:16 2018<br>
@@ -3952,9 +3952,9 @@ int HexagonInstrInfo::<wbr>getOperandLatency(<br>
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();<br>
<br>
// Get DefIdx and UseIdx for super registers.<br>
- MachineOperand DefMO = DefMI.getOperand(DefIdx);<br>
+ const MachineOperand &DefMO = DefMI.getOperand(DefIdx);<br>
<br>
- if (HRI.isPhysicalRegister(DefMO.<wbr>getReg())) {<br>
+ if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.<wbr>getReg())) {<br>
if (DefMO.isImplicit()) {<br>
for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {<br>
int Idx = DefMI.<wbr>findRegisterDefOperandIdx(*SR, false, false, &HRI);<br>
@@ -3965,7 +3965,7 @@ int HexagonInstrInfo::<wbr>getOperandLatency(<br>
}<br>
}<br>
<br>
- MachineOperand UseMO = UseMI.getOperand(UseIdx);<br>
+ const MachineOperand &UseMO = UseMI.getOperand(UseIdx);<br>
if (UseMO.isImplicit()) {<br>
for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {<br>
int Idx = UseMI.<wbr>findRegisterUseOperandIdx(*SR, false, &HRI);<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>HexagonSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=328542&r1=328541&r2=328542&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Hexagon/HexagonSubtarget.cpp?<wbr>rev=328542&r1=328541&r2=<wbr>328542&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>HexagonSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>HexagonSubtarget.cpp Mon Mar 26 09:33:16 2018<br>
@@ -353,22 +353,27 @@ void HexagonSubtarget::<wbr>adjustSchedDepend<br>
if (!hasV60TOps())<br>
return;<br>
<br>
- // If it's a REG_SEQUENCE, use its destination instruction to determine<br>
+ // Set the latency for a copy to zero since we hope that is will get removed.<br>
+ if (DstInst->isCopy())<br>
+ Dep.setLatency(0);<br>
+<br>
+ // If it's a REG_SEQUENCE/COPY, use its destination instruction to determine<br>
// the correct latency.<br>
- if (DstInst->isRegSequence() && Dst->NumSuccs == 1) {<br>
- unsigned RSeqReg = DstInst->getOperand(0).getReg(<wbr>);<br>
- MachineInstr *RSeqDst = Dst->Succs[0].getSUnit()-><wbr>getInstr();<br>
+ if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) {<br>
+ unsigned DReg = DstInst->getOperand(0).getReg(<wbr>);<br>
+ MachineInstr *DDst = Dst->Succs[0].getSUnit()-><wbr>getInstr();<br>
unsigned UseIdx = -1;<br>
- for (unsigned OpNum = 0; OpNum < RSeqDst->getNumOperands(); OpNum++) {<br>
- const MachineOperand &MO = RSeqDst->getOperand(OpNum);<br>
- if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == RSeqReg) {<br>
+ for (unsigned OpNum = 0; OpNum < DDst->getNumOperands(); OpNum++) {<br>
+ const MachineOperand &MO = DDst->getOperand(OpNum);<br>
+ if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {<br>
UseIdx = OpNum;<br>
break;<br>
}<br>
}<br>
- unsigned RSeqLatency = (InstrInfo.getOperandLatency(&<wbr>InstrItins, *SrcInst,<br>
- 0, *RSeqDst, UseIdx));<br>
- Dep.setLatency(RSeqLatency);<br>
+ int DLatency = (InstrInfo.getOperandLatency(&<wbr>InstrItins, *SrcInst,<br>
+ 0, *DDst, UseIdx));<br>
+ DLatency = std::max(DLatency, 0);<br>
+ Dep.setLatency((unsigned)<wbr>DLatency);<br>
}<br>
<br>
// Try to schedule uses near definitions to generate .cur.<br>
@@ -448,8 +453,7 @@ void HexagonSubtarget::<wbr>restoreLatency(SU<br>
<br>
// For some instructions (ex: COPY), we might end up with < 0 latency<br>
// as they don't have any Itinerary class associated with them.<br>
- if (Latency <= 0)<br>
- Latency = 1;<br>
+ Latency = std::max(Latency, 0);<br>
<br>
I.setLatency(Latency);<br>
updateLatency(*SrcI, *DstI, I);<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>Hexagon/sdr-reg-profit.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/sdr-reg-profit.ll?rev=328542&r1=328541&r2=328542&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/sdr-reg-<wbr>profit.ll?rev=328542&r1=<wbr>328541&r2=328542&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>Hexagon/sdr-reg-profit.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>Hexagon/sdr-reg-profit.ll Mon Mar 26 09:33:16 2018<br>
@@ -1,3 +1,5 @@<br>
+; XFAIL: *<br>
+; This requires further patches.<br>
; RUN: llc -march=hexagon < %s | FileCheck %s<br>
;<br>
; Split all andp/orp instructions (by boosting the profitability of their<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-phi-ref.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-phi-ref.ll?rev=328542&r1=328541&r2=328542&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Hexagon/swp-phi-ref.<wbr>ll?rev=328542&r1=328541&r2=<wbr>328542&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-phi-ref.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>Hexagon/swp-phi-ref.ll Mon Mar 26 09:33:16 2018<br>
@@ -8,9 +8,10 @@<br>
; correct value. We need to do this even if we haven't generated the<br>
; kernel code for the other Phi yet.<br>
<br>
-; CHECK: [[REG0:(v[0-9]+)]] = [[REG1:(v[0-9]+)]]<br>
+; CHECK: v[[REG0:[0-9]+]] = v[[REG1:[0-9]+]]<br>
; CHECK: loop0<br>
-; CHECK: [[REG0]] = [[REG1]]<br>
+; Check for copy REG0 = REG1 (via vcombine):<br>
+; CHECK: v{{[0-9]+}}:[[REG0]] = vcombine(v{{[0-9]+}},v[[REG1]]<wbr>)<br>
; CHECK: endloop0<br>
<br>
; Function Attrs: nounwind<br>
<br>
<br>
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</blockquote></div><br></div></div>