[llvm] r329568 - [X86][MMX] Fix missing itinerary for PALIGNR

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Apr  9 06:52:33 2018
New Revision: 329568

URL: http://llvm.org/viewvc/llvm-project?rev=329568&view=rev
Log:
[X86][MMX] Fix missing itinerary for PALIGNR

Modified:
    llvm/trunk/lib/Target/X86/X86InstrMMX.td
    llvm/trunk/test/CodeGen/X86/mmx-schedule.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=329568&r1=329567&r2=329568&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Mon Apr  9 06:52:33 2018
@@ -183,14 +183,14 @@ multiclass ssse3_palign_mm<string asm, I
   def rri  : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
       (ins VR64:$src1, VR64:$src2, u8imm:$src3),
       !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
-      [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>,
-      Sched<[WriteShuffle]>;
+      [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))],
+      IIC_MMX_PSHUF>, Sched<[WriteShuffle]>;
   def rmi  : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
       (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
       !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
       [(set VR64:$dst, (IntId VR64:$src1,
-                       (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>,
-      Sched<[WriteShuffleLd, ReadAfterLd]>;
+                       (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))],
+      IIC_MMX_PSHUF>, Sched<[WriteShuffleLd, ReadAfterLd]>;
 }
 
 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,

Modified: llvm/trunk/test/CodeGen/X86/mmx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-schedule.ll?rev=329568&r1=329567&r2=329568&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mmx-schedule.ll Mon Apr  9 06:52:33 2018
@@ -2127,8 +2127,8 @@ define i64 @test_palignr(x86_mmx %a0, x8
 ;
 ; ATOM-LABEL: test_palignr:
 ; ATOM:       # %bb.0:
-; ATOM-NEXT:    palignr $1, %mm1, %mm0 # sched: [0:?]
-; ATOM-NEXT:    palignr $1, (%rdi), %mm0 # sched: [0:?]
+; ATOM-NEXT:    palignr $1, %mm1, %mm0 # sched: [1:1.00]
+; ATOM-NEXT:    palignr $1, (%rdi), %mm0 # sched: [1:1.00]
 ; ATOM-NEXT:    movq %mm0, %rax # sched: [3:3.00]
 ; ATOM-NEXT:    retq # sched: [79:39.50]
 ;