[PATCH] D45380: [X86] Add SchedWrites for CMOV and SETCC. Use them to remove InstRWs.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:145
+defm : JWriteResIntPair<WriteCMOV,  [JALU01], 1>; // Conditional move.
+def  : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
+
----------------
craig.topper wrote:
> RKSimon wrote:
> > Move the WriteSETCCStore def into the models so we don't get the regression on btver2 tests?
> You mean make it a regular SchedWrite and not a WriteSequence?
If you can, otherwise please can you add a InstRW like znver1 has to btver2?


Repository:
  rL LLVM

https://reviews.llvm.org/D45380