[PATCH] D45203: [X86] VRNDSCALE* folding from masked and single-value ffloor and fceil patterns

[Mikhail Dvoretckii via Phabricator via llvm-commits]

mike.dvoretsky added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:30511
+  return DAG.getNode(X86ISD::VRNDSCALES, DL, VT, N1, N0.getOperand(0),
+                     DAG.getConstant(Imm, DL, MVT::i32));
+}
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craig.topper wrote:
> Can we just do this with isel patterns like we do for ADDSS?
I've considered that, but decided to fold it here. To do it in .td patterns we'd need to add 4 new patterns in 2 separate files. 32 and 64 bit patterns would need to be added for VROUNDS* on AVX and ROUNDS* on SSE4.1. Writing this pattern here both makes it easier to track and produces less check complexity.


https://reviews.llvm.org/D45203