[PATCH] D45203: [X86] VRNDSCALE* folding from masked and single-value ffloor and fceil patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:30511
+  return DAG.getNode(X86ISD::VRNDSCALES, DL, VT, N1, N0.getOperand(0),
+                     DAG.getConstant(Imm, DL, MVT::i32));
+}
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Can we just do this with isel patterns like we do for ADDSS?


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Comment at: llvm/test/CodeGen/X86/vec_floor.ll:873
+; AVX512-NEXT:    retq
+  %call = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x)
+  %res = select <16 x i1> %k, <16 x float> %call, <16 x float> %y
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Can you generate %k from a compare instruction rather than passing in a X x i1 type. It will make the code a little cleaner since we won't have to extend and split the mask in such crazy ways.


https://reviews.llvm.org/D45203